Flash Configuration Field settings. Default values are always loaded from application first.
FCF can be provided in one of three ways:
1. As a nested dictionary under the 'fcf' key - copy values directly from the FCF.YAML template
2. As a path to a YAML file containing FCF configuration - use 'fcf: path/to/fcf.yaml'
3. As a path to a binary FCF file - use 'fcf: path/to/fcf.bin'
If any FCF configuration is provided, it will update the application values accordingly. The binary option completely replaces the FCF content, while the YAML and dictionary options selectively update FCF register values.
NXP chip family identifier.
Revision of silicon. The 'latest' name, means most current revision.
Definition if application is Execute in Place(XiP) or loaded to RAM during reset sequence.
Specification of final master boot image authentication.
The path for result binary file.
The input application image to by modified to Master Boot Image.
Offset: 0x00000000, Width: 32b; Tag: Magic number to verify bootloader configuration is valid. Must be set to 'kcfg' (0x6766636B).
Offset: 0x00000000, Width: 32b; Tag: Magic number to verify bootloader configuration is valid. Must be set to 'kcfg' (0x6766636B).
Offset: 0x00000010, Width: 8b; Configuration bitfields of peripherals to enable. Bootloader will enable the peripheral if corresponding bit is set to 1.
Offset: 0b, Width: 1b, Enable LPUART peripheral
- DISABLE, (0): Disable LPUART peripheral
- ENABLE, (1): Enable LPUART peripheral
Offset: 1b, Width: 1b, Enable I2C peripheral
- DISABLE, (0): Disable I2C peripheral
- ENABLE, (1): Enable I2C peripheral
Offset: 2b, Width: 1b, Enable SPI peripheral
- DISABLE, (0): Disable SPI peripheral
- ENABLE, (1): Enable SPI peripheral
Offset: 3b, Width: 1b, N/A
Offset: 3b, Width: 1b, N/A
Offset: 4b, Width: 1b, N/A
Offset: 4b, Width: 1b, N/A
Offset: 5b, Width: 3b, N/A
Offset: 5b, Width: 3b, N/A
Offset: 0b, Width: 1b, Enable LPUART peripheral
- DISABLE, (0): Disable LPUART peripheral
- ENABLE, (1): Enable LPUART peripheral
Offset: 1b, Width: 1b, Enable I2C peripheral
- DISABLE, (0): Disable I2C peripheral
- ENABLE, (1): Enable I2C peripheral
Offset: 2b, Width: 1b, Enable SPI peripheral
- DISABLE, (0): Disable SPI peripheral
- ENABLE, (1): Enable SPI peripheral
Offset: 3b, Width: 1b, N/A
Offset: 3b, Width: 1b, N/A
Offset: 4b, Width: 1b, N/A
Offset: 4b, Width: 1b, N/A
Offset: 5b, Width: 3b, N/A
Offset: 5b, Width: 3b, N/A
Offset: 0x00000010, Width: 8b; Configuration bitfields of peripherals to enable. Bootloader will enable the peripheral if corresponding bit is set to 1.
Offset: 0b, Width: 1b, Enable LPUART peripheral
- DISABLE, (0): Disable LPUART peripheral
- ENABLE, (1): Enable LPUART peripheral
Offset: 1b, Width: 1b, Enable I2C peripheral
- DISABLE, (0): Disable I2C peripheral
- ENABLE, (1): Enable I2C peripheral
Offset: 2b, Width: 1b, Enable SPI peripheral
- DISABLE, (0): Disable SPI peripheral
- ENABLE, (1): Enable SPI peripheral
Offset: 3b, Width: 1b, N/A
Offset: 3b, Width: 1b, N/A
Offset: 4b, Width: 1b, N/A
Offset: 4b, Width: 1b, N/A
Offset: 5b, Width: 3b, N/A
Offset: 5b, Width: 3b, N/A
Offset: 0b, Width: 1b, Enable LPUART peripheral
- DISABLE, (0): Disable LPUART peripheral
- ENABLE, (1): Enable LPUART peripheral
Offset: 1b, Width: 1b, Enable I2C peripheral
- DISABLE, (0): Disable I2C peripheral
- ENABLE, (1): Enable I2C peripheral
Offset: 2b, Width: 1b, Enable SPI peripheral
- DISABLE, (0): Disable SPI peripheral
- ENABLE, (1): Enable SPI peripheral
Offset: 3b, Width: 1b, N/A
Offset: 3b, Width: 1b, N/A
Offset: 4b, Width: 1b, N/A
Offset: 4b, Width: 1b, N/A
Offset: 5b, Width: 3b, N/A
Offset: 5b, Width: 3b, N/A
Offset: 0x00000011, Width: 8b; Configuration of I2C slave address
Offset: 0b, Width: 8b, If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C slave address.
Offset: 0b, Width: 8b, If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C slave address.
Offset: 0b, Width: 8b, If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C slave address.
Offset: 0b, Width: 8b, If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C slave address.
Offset: 0x00000011, Width: 8b; Configuration of I2C slave address
Offset: 0b, Width: 8b, If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C slave address.
Offset: 0b, Width: 8b, If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C slave address.
Offset: 0b, Width: 8b, If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C slave address.
Offset: 0b, Width: 8b, If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C slave address.
Offset: 0x00000012, Width: 16b; Timeout in milliseconds for active peripheral detection. If 0xFFFF, defaults to 5 seconds.
Offset: 0b, Width: 16b, Timeout in milliseconds for active peripheral detection. If 0xFFFF, defaults to 5 seconds.
Offset: 0b, Width: 16b, Timeout in milliseconds for active peripheral detection. If 0xFFFF, defaults to 5 seconds.
Offset: 0b, Width: 16b, Timeout in milliseconds for active peripheral detection. If 0xFFFF, defaults to 5 seconds.
Offset: 0b, Width: 16b, Timeout in milliseconds for active peripheral detection. If 0xFFFF, defaults to 5 seconds.
Offset: 0x00000012, Width: 16b; Timeout in milliseconds for active peripheral detection. If 0xFFFF, defaults to 5 seconds.
Offset: 0b, Width: 16b, Timeout in milliseconds for active peripheral detection. If 0xFFFF, defaults to 5 seconds.
Offset: 0b, Width: 16b, Timeout in milliseconds for active peripheral detection. If 0xFFFF, defaults to 5 seconds.
Offset: 0b, Width: 16b, Timeout in milliseconds for active peripheral detection. If 0xFFFF, defaults to 5 seconds.
Offset: 0b, Width: 16b, Timeout in milliseconds for active peripheral detection. If 0xFFFF, defaults to 5 seconds.
Offset: 0x0000001C, Width: 8b; Configuration clockFlags field. The flags in the clockFlags configuration field are enabled if the corresponding bit is cleared (0).
Offset: 0b, Width: 1b, Enable high speed mode (i.e., 48 MHz).
- ENABLE, (0): Enable high speed.
- DISABLE, (1): Disable high speed.
Offset: 0b, Width: 1b, Enable high speed mode (i.e., 48 MHz).
- ENABLE, (0): Enable high speed.
- DISABLE, (1): Disable high speed.
Offset: 1b, Width: 7b, N/A
Offset: 1b, Width: 7b, N/A
Offset: 0b, Width: 1b, Enable high speed mode (i.e., 48 MHz).
- ENABLE, (0): Enable high speed.
- DISABLE, (1): Disable high speed.
Offset: 0b, Width: 1b, Enable high speed mode (i.e., 48 MHz).
- ENABLE, (0): Enable high speed.
- DISABLE, (1): Disable high speed.
Offset: 1b, Width: 7b, N/A
Offset: 1b, Width: 7b, N/A
Offset: 0x0000001C, Width: 8b; Configuration clockFlags field. The flags in the clockFlags configuration field are enabled if the corresponding bit is cleared (0).
Offset: 0b, Width: 1b, Enable high speed mode (i.e., 48 MHz).
- ENABLE, (0): Enable high speed.
- DISABLE, (1): Disable high speed.
Offset: 0b, Width: 1b, Enable high speed mode (i.e., 48 MHz).
- ENABLE, (0): Enable high speed.
- DISABLE, (1): Disable high speed.
Offset: 1b, Width: 7b, N/A
Offset: 1b, Width: 7b, N/A
Offset: 0b, Width: 1b, Enable high speed mode (i.e., 48 MHz).
- ENABLE, (0): Enable high speed.
- DISABLE, (1): Disable high speed.
Offset: 0b, Width: 1b, Enable high speed mode (i.e., 48 MHz).
- ENABLE, (0): Enable high speed.
- DISABLE, (1): Disable high speed.
Offset: 1b, Width: 7b, N/A
Offset: 1b, Width: 7b, N/A
Offset: 0x0000001D, Width: 8b; Clock divider configuration
Offset: 0b, Width: 8b, Inverted value of the divider to use for core and bus clocks when in high speed mode.
Offset: 0b, Width: 8b, Inverted value of the divider to use for core and bus clocks when in high speed mode.
Offset: 0b, Width: 8b, Inverted value of the divider to use for core and bus clocks when in high speed mode.
Offset: 0b, Width: 8b, Inverted value of the divider to use for core and bus clocks when in high speed mode.
Offset: 0x0000001D, Width: 8b; Clock divider configuration
Offset: 0b, Width: 8b, Inverted value of the divider to use for core and bus clocks when in high speed mode.
Offset: 0b, Width: 8b, Inverted value of the divider to use for core and bus clocks when in high speed mode.
Offset: 0b, Width: 8b, Inverted value of the divider to use for core and bus clocks when in high speed mode.
Offset: 0b, Width: 8b, Inverted value of the divider to use for core and bus clocks when in high speed mode.
Path to BCA configuration or binary file
Offset: 0x00000000, Width: 64b; Backdoor Comparison Key. Refer to Verify Backdoor Access Key Command and Unsecuring the Chip Using Backdoor Key Access.
Offset: 0x00000000, Width: 64b; Backdoor Comparison Key. Refer to Verify Backdoor Access Key Command and Unsecuring the Chip Using Backdoor Key Access.
Offset: 0x00000008, Width: 32b; Program flash protection bytes. Refer to the description of the Program Flash Protection Registers (FPROT0-3).
Offset: 0b, Width: 8b, Program Flash Protection Registers (FPROT3)
Offset: 8b, Width: 8b, Program Flash Protection Registers (FPROT2)
Offset: 16b, Width: 8b, Program Flash Protection Registers (FPROT1)
Offset: 24b, Width: 8b, Program Flash Protection Registers (FPROT0)
Offset: 0b, Width: 8b, Program Flash Protection Registers (FPROT3)
Offset: 8b, Width: 8b, Program Flash Protection Registers (FPROT2)
Offset: 16b, Width: 8b, Program Flash Protection Registers (FPROT1)
Offset: 24b, Width: 8b, Program Flash Protection Registers (FPROT0)
Offset: 0x00000008, Width: 32b; Program flash protection bytes. Refer to the description of the Program Flash Protection Registers (FPROT0-3).
Offset: 0b, Width: 8b, Program Flash Protection Registers (FPROT3)
Offset: 8b, Width: 8b, Program Flash Protection Registers (FPROT2)
Offset: 16b, Width: 8b, Program Flash Protection Registers (FPROT1)
Offset: 24b, Width: 8b, Program Flash Protection Registers (FPROT0)
Offset: 0b, Width: 8b, Program Flash Protection Registers (FPROT3)
Offset: 8b, Width: 8b, Program Flash Protection Registers (FPROT2)
Offset: 16b, Width: 8b, Program Flash Protection Registers (FPROT1)
Offset: 24b, Width: 8b, Program Flash Protection Registers (FPROT0)
Offset: 0x0000000C, Width: 8b; Flash security byte. Refer to the description of the Flash Security Register (FSEC).
Offset: 0b, Width: 2b, Flash Security.
- SECURE0, (0): MCU security status is secure.
- SECURE, (1): MCU security status is secure.
- UNSECURE, (2): MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)
- SECURE3, (3): MCU security status is secure.
Offset: 6b, Width: 2b, Backdoor Key Security Enable. Enables or disables backdoor key access to the flash memory module.
- DISABLED0, (0): Backdoor key access disabled
- DISABLED, (1): Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
- ENABLED, (2): Backdoor key access enabled
- DISABLED3, (3): Backdoor key access disabled
Offset: 0b, Width: 2b, Flash Security.
- SECURE0, (0): MCU security status is secure.
- SECURE, (1): MCU security status is secure.
- UNSECURE, (2): MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)
- SECURE3, (3): MCU security status is secure.
Offset: 6b, Width: 2b, Backdoor Key Security Enable. Enables or disables backdoor key access to the flash memory module.
- DISABLED0, (0): Backdoor key access disabled
- DISABLED, (1): Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
- ENABLED, (2): Backdoor key access enabled
- DISABLED3, (3): Backdoor key access disabled
Offset: 0x0000000C, Width: 8b; Flash security byte. Refer to the description of the Flash Security Register (FSEC).
Offset: 0b, Width: 2b, Flash Security.
- SECURE0, (0): MCU security status is secure.
- SECURE, (1): MCU security status is secure.
- UNSECURE, (2): MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)
- SECURE3, (3): MCU security status is secure.
Offset: 6b, Width: 2b, Backdoor Key Security Enable. Enables or disables backdoor key access to the flash memory module.
- DISABLED0, (0): Backdoor key access disabled
- DISABLED, (1): Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
- ENABLED, (2): Backdoor key access enabled
- DISABLED3, (3): Backdoor key access disabled
Offset: 0b, Width: 2b, Flash Security.
- SECURE0, (0): MCU security status is secure.
- SECURE, (1): MCU security status is secure.
- UNSECURE, (2): MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)
- SECURE3, (3): MCU security status is secure.
Offset: 6b, Width: 2b, Backdoor Key Security Enable. Enables or disables backdoor key access to the flash memory module.
- DISABLED0, (0): Backdoor key access disabled
- DISABLED, (1): Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
- ENABLED, (2): Backdoor key access enabled
- DISABLED3, (3): Backdoor key access disabled
Offset: 0x0000000D, Width: 8b; Flash nonvolatile option byte. Refer to the description of the Flash Option Register (FOPT).
Offset: 0b, Width: 1b, Configure Core and system clock divider (OUTDIV1) value on exit from reset. Together with LPBOOT[1], controls the reset value of OUTDIV1 value in SIMCLKDIV1 register, and the state of the RUNM register in SMCPMCTRL.
Larger divide value selections produce lower average power consumption during POR, VLLSx recoveries and reset sequencing and after reset exit. The recovery times are also extended if the FASTINIT option is not selected.
- DIVBY8OR2, (0): VLPR mode: Core and system clock divider (OUTDIV1) is 0x7 (divide by 8).
RUN mode: Core and system clock divider (OUTDIV1) is 0x1 (divide by 2).
- DIVBY4OR_1, (1): VLPR mode: Core and system clock divider (OUTDIV1) is 0x3 (divide by 4).
RUN mode: Core and system clock divider (OUTDIV1) is 0x0 (divide by 1).
Offset: 1b, Width: 1b, External pin selects boot options.
- FORCEFROMROM, (0): Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin. RESET pin must be enabled (FOPT[RESETPINCFG] = 1) when this option is selected. NMI pin is sampled at the end of reset (when reset pin negates). If BOOTCFG0 pin is not asserted, Boot source configured by FOPT[7:6] (BOOTSRCSEL) bits.
- BOOTSRCSEL, (1): Boot source configured by FOPT[7:6] (BOOTSRC_SEL) bits.
Offset: 2b, Width: 1b, Enables/disables control for the NMI function.
- DISABLE, (0): NMI interrupts are always blocked. The associated pin continues to default to NMI pin controls with internal pullup enabled. When NMI pin function is disabled, it cannot be used as a source for low-power mode wake-up.
- ENABLE, (1): NMI_b pin/interrupts reset default to enabled.
Offset: 3b, Width: 1b, Enables/disables control for the RESET pin.
- DISABLE, (0): RESET pin is disabled following a POR and cannot be enabled as reset function.
- ENABLE, (1): RESET_b pin is dedicated. The port is configured with pullup enabled, open drain, passive filter enabled.
Offset: 4b, Width: 1b, Configure device for VLPR or RUN mode on exit from reset. Together with LPBOOT[0], controls the reset value of OUTDIV1 value in SIMCLKDIV1 register, and the state of the RUNM register in SMCPMCTRL.
- VLPRMODE, (0): Device is configured for VLPR mode on exit from reset.
- RUNMODE, (1): Device is configured for RUN mode on exit from reset.
Offset: 5b, Width: 1b, Selects initialization speed on POR, VLLSx, and any system reset.
- DISABLE, (0): Slower initialization: The flash initialization will be slower with the benefit of reduced average current during this time. The duration of the recovery will be controlled by the clock divider selection determined by the LPBOOT setting.
- ENABLE, (1): Fast Initialization: The flash has faster recoveries at the expense of higher current during these times.
Offset: 6b, Width: 2b, Boot Source Selection: these bits select the boot sources if boot pin option bit BOOTPINOPT = 1
- FLASH, (0): Boot from Flash
- ROM2, (2): Boot from ROM
- ROM, (3): Boot from ROM
Offset: 0b, Width: 1b, Configure Core and system clock divider (OUTDIV1) value on exit from reset. Together with LPBOOT[1], controls the reset value of OUTDIV1 value in SIMCLKDIV1 register, and the state of the RUNM register in SMCPMCTRL.
Larger divide value selections produce lower average power consumption during POR, VLLSx recoveries and reset sequencing and after reset exit. The recovery times are also extended if the FASTINIT option is not selected.
- DIVBY8OR2, (0): VLPR mode: Core and system clock divider (OUTDIV1) is 0x7 (divide by 8).
RUN mode: Core and system clock divider (OUTDIV1) is 0x1 (divide by 2).
- DIVBY4OR_1, (1): VLPR mode: Core and system clock divider (OUTDIV1) is 0x3 (divide by 4).
RUN mode: Core and system clock divider (OUTDIV1) is 0x0 (divide by 1).
Offset: 1b, Width: 1b, External pin selects boot options.
- FORCEFROMROM, (0): Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin. RESET pin must be enabled (FOPT[RESETPINCFG] = 1) when this option is selected. NMI pin is sampled at the end of reset (when reset pin negates). If BOOTCFG0 pin is not asserted, Boot source configured by FOPT[7:6] (BOOTSRCSEL) bits.
- BOOTSRCSEL, (1): Boot source configured by FOPT[7:6] (BOOTSRC_SEL) bits.
Offset: 2b, Width: 1b, Enables/disables control for the NMI function.
- DISABLE, (0): NMI interrupts are always blocked. The associated pin continues to default to NMI pin controls with internal pullup enabled. When NMI pin function is disabled, it cannot be used as a source for low-power mode wake-up.
- ENABLE, (1): NMI_b pin/interrupts reset default to enabled.
Offset: 3b, Width: 1b, Enables/disables control for the RESET pin.
- DISABLE, (0): RESET pin is disabled following a POR and cannot be enabled as reset function.
- ENABLE, (1): RESET_b pin is dedicated. The port is configured with pullup enabled, open drain, passive filter enabled.
Offset: 4b, Width: 1b, Configure device for VLPR or RUN mode on exit from reset. Together with LPBOOT[0], controls the reset value of OUTDIV1 value in SIMCLKDIV1 register, and the state of the RUNM register in SMCPMCTRL.
- VLPRMODE, (0): Device is configured for VLPR mode on exit from reset.
- RUNMODE, (1): Device is configured for RUN mode on exit from reset.
Offset: 5b, Width: 1b, Selects initialization speed on POR, VLLSx, and any system reset.
- DISABLE, (0): Slower initialization: The flash initialization will be slower with the benefit of reduced average current during this time. The duration of the recovery will be controlled by the clock divider selection determined by the LPBOOT setting.
- ENABLE, (1): Fast Initialization: The flash has faster recoveries at the expense of higher current during these times.
Offset: 6b, Width: 2b, Boot Source Selection: these bits select the boot sources if boot pin option bit BOOTPINOPT = 1
- FLASH, (0): Boot from Flash
- ROM2, (2): Boot from ROM
- ROM, (3): Boot from ROM
Offset: 0x0000000D, Width: 8b; Flash nonvolatile option byte. Refer to the description of the Flash Option Register (FOPT).
Offset: 0b, Width: 1b, Configure Core and system clock divider (OUTDIV1) value on exit from reset. Together with LPBOOT[1], controls the reset value of OUTDIV1 value in SIMCLKDIV1 register, and the state of the RUNM register in SMCPMCTRL.
Larger divide value selections produce lower average power consumption during POR, VLLSx recoveries and reset sequencing and after reset exit. The recovery times are also extended if the FASTINIT option is not selected.
- DIVBY8OR2, (0): VLPR mode: Core and system clock divider (OUTDIV1) is 0x7 (divide by 8).
RUN mode: Core and system clock divider (OUTDIV1) is 0x1 (divide by 2).
- DIVBY4OR_1, (1): VLPR mode: Core and system clock divider (OUTDIV1) is 0x3 (divide by 4).
RUN mode: Core and system clock divider (OUTDIV1) is 0x0 (divide by 1).
Offset: 1b, Width: 1b, External pin selects boot options.
- FORCEFROMROM, (0): Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin. RESET pin must be enabled (FOPT[RESETPINCFG] = 1) when this option is selected. NMI pin is sampled at the end of reset (when reset pin negates). If BOOTCFG0 pin is not asserted, Boot source configured by FOPT[7:6] (BOOTSRCSEL) bits.
- BOOTSRCSEL, (1): Boot source configured by FOPT[7:6] (BOOTSRC_SEL) bits.
Offset: 2b, Width: 1b, Enables/disables control for the NMI function.
- DISABLE, (0): NMI interrupts are always blocked. The associated pin continues to default to NMI pin controls with internal pullup enabled. When NMI pin function is disabled, it cannot be used as a source for low-power mode wake-up.
- ENABLE, (1): NMI_b pin/interrupts reset default to enabled.
Offset: 3b, Width: 1b, Enables/disables control for the RESET pin.
- DISABLE, (0): RESET pin is disabled following a POR and cannot be enabled as reset function.
- ENABLE, (1): RESET_b pin is dedicated. The port is configured with pullup enabled, open drain, passive filter enabled.
Offset: 4b, Width: 1b, Configure device for VLPR or RUN mode on exit from reset. Together with LPBOOT[0], controls the reset value of OUTDIV1 value in SIMCLKDIV1 register, and the state of the RUNM register in SMCPMCTRL.
- VLPRMODE, (0): Device is configured for VLPR mode on exit from reset.
- RUNMODE, (1): Device is configured for RUN mode on exit from reset.
Offset: 5b, Width: 1b, Selects initialization speed on POR, VLLSx, and any system reset.
- DISABLE, (0): Slower initialization: The flash initialization will be slower with the benefit of reduced average current during this time. The duration of the recovery will be controlled by the clock divider selection determined by the LPBOOT setting.
- ENABLE, (1): Fast Initialization: The flash has faster recoveries at the expense of higher current during these times.
Offset: 6b, Width: 2b, Boot Source Selection: these bits select the boot sources if boot pin option bit BOOTPINOPT = 1
- FLASH, (0): Boot from Flash
- ROM2, (2): Boot from ROM
- ROM, (3): Boot from ROM
Offset: 0b, Width: 1b, Configure Core and system clock divider (OUTDIV1) value on exit from reset. Together with LPBOOT[1], controls the reset value of OUTDIV1 value in SIMCLKDIV1 register, and the state of the RUNM register in SMCPMCTRL.
Larger divide value selections produce lower average power consumption during POR, VLLSx recoveries and reset sequencing and after reset exit. The recovery times are also extended if the FASTINIT option is not selected.
- DIVBY8OR2, (0): VLPR mode: Core and system clock divider (OUTDIV1) is 0x7 (divide by 8).
RUN mode: Core and system clock divider (OUTDIV1) is 0x1 (divide by 2).
- DIVBY4OR_1, (1): VLPR mode: Core and system clock divider (OUTDIV1) is 0x3 (divide by 4).
RUN mode: Core and system clock divider (OUTDIV1) is 0x0 (divide by 1).
Offset: 1b, Width: 1b, External pin selects boot options.
- FORCEFROMROM, (0): Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin. RESET pin must be enabled (FOPT[RESETPINCFG] = 1) when this option is selected. NMI pin is sampled at the end of reset (when reset pin negates). If BOOTCFG0 pin is not asserted, Boot source configured by FOPT[7:6] (BOOTSRCSEL) bits.
- BOOTSRCSEL, (1): Boot source configured by FOPT[7:6] (BOOTSRC_SEL) bits.
Offset: 2b, Width: 1b, Enables/disables control for the NMI function.
- DISABLE, (0): NMI interrupts are always blocked. The associated pin continues to default to NMI pin controls with internal pullup enabled. When NMI pin function is disabled, it cannot be used as a source for low-power mode wake-up.
- ENABLE, (1): NMI_b pin/interrupts reset default to enabled.
Offset: 3b, Width: 1b, Enables/disables control for the RESET pin.
- DISABLE, (0): RESET pin is disabled following a POR and cannot be enabled as reset function.
- ENABLE, (1): RESET_b pin is dedicated. The port is configured with pullup enabled, open drain, passive filter enabled.
Offset: 4b, Width: 1b, Configure device for VLPR or RUN mode on exit from reset. Together with LPBOOT[0], controls the reset value of OUTDIV1 value in SIMCLKDIV1 register, and the state of the RUNM register in SMCPMCTRL.
- VLPRMODE, (0): Device is configured for VLPR mode on exit from reset.
- RUNMODE, (1): Device is configured for RUN mode on exit from reset.
Offset: 5b, Width: 1b, Selects initialization speed on POR, VLLSx, and any system reset.
- DISABLE, (0): Slower initialization: The flash initialization will be slower with the benefit of reduced average current during this time. The duration of the recovery will be controlled by the clock divider selection determined by the LPBOOT setting.
- ENABLE, (1): Fast Initialization: The flash has faster recoveries at the expense of higher current during these times.
Offset: 6b, Width: 2b, Boot Source Selection: these bits select the boot sources if boot pin option bit BOOTPINOPT = 1
- FLASH, (0): Boot from Flash
- ROM2, (2): Boot from ROM
- ROM, (3): Boot from ROM
Path to FCF configuration or binary file