Flash Configuration Field settings. Default values are always loaded from application first.
FCF can be provided in one of three ways:
1. As a nested dictionary under the 'fcf' key - copy values directly from the FCF.YAML template
2. As a path to a YAML file containing FCF configuration - use 'fcf: path/to/fcf.yaml'
3. As a path to a binary FCF file - use 'fcf: path/to/fcf.bin'
If any FCF configuration is provided, it will update the application values accordingly. The binary option completely replaces the FCF content, while the YAML and dictionary options selectively update FCF register values.
NXP chip family identifier.
Revision of silicon. The 'latest' name, means most current revision.
Definition if application is Execute in Place(XiP) or loaded to RAM during reset sequence.
Specification of final master boot image authentication.
The path for result binary file.
The input application image to by modified to Master Boot Image.
Offset: 0x00000000, Width: 32b; Tag: Magic number to verify bootloader configuration is valid. Must be set to 'KCFG'
Offset: 0x00000000, Width: 32b; Tag: Magic number to verify bootloader configuration is valid. Must be set to 'KCFG'
Offset: 0x00000004, Width: 32b; Start address for application image CRC check
Offset: 0x00000004, Width: 32b; Start address for application image CRC check
Offset: 0x00000008, Width: 32b; Byte count for application image CRC check
Offset: 0x00000008, Width: 32b; Byte count for application image CRC check
Offset: 0x0000000C, Width: 32b; Expected CRC value for application CRC check
Offset: 0x0000000C, Width: 32b; Expected CRC value for application CRC check
Offset: 0x00000010, Width: 8b; Bitfield of peripherals to enable. Bootloader will enable the peripheral if corresponding bit is set to 1
Offset: 0b, Width: 1b, Enable UART/SCI peripheral
- DISABLE, (0): Disable UART/SCI peripheral
- ENABLE, (1): Enable UART/SCI peripheral
Offset: 1b, Width: 1b, Enable LPI2C peripheral
- DISABLE, (0): Disable LPI2C peripheral
- ENABLE, (1): Enable LPI2C peripheral
Offset: 2b, Width: 6b, N/A
Offset: 2b, Width: 6b, N/A
Offset: 0b, Width: 1b, Enable UART/SCI peripheral
- DISABLE, (0): Disable UART/SCI peripheral
- ENABLE, (1): Enable UART/SCI peripheral
Offset: 1b, Width: 1b, Enable LPI2C peripheral
- DISABLE, (0): Disable LPI2C peripheral
- ENABLE, (1): Enable LPI2C peripheral
Offset: 2b, Width: 6b, N/A
Offset: 2b, Width: 6b, N/A
Offset: 0x00000010, Width: 8b; Bitfield of peripherals to enable. Bootloader will enable the peripheral if corresponding bit is set to 1
Offset: 0b, Width: 1b, Enable UART/SCI peripheral
- DISABLE, (0): Disable UART/SCI peripheral
- ENABLE, (1): Enable UART/SCI peripheral
Offset: 1b, Width: 1b, Enable LPI2C peripheral
- DISABLE, (0): Disable LPI2C peripheral
- ENABLE, (1): Enable LPI2C peripheral
Offset: 2b, Width: 6b, N/A
Offset: 2b, Width: 6b, N/A
Offset: 0b, Width: 1b, Enable UART/SCI peripheral
- DISABLE, (0): Disable UART/SCI peripheral
- ENABLE, (1): Enable UART/SCI peripheral
Offset: 1b, Width: 1b, Enable LPI2C peripheral
- DISABLE, (0): Disable LPI2C peripheral
- ENABLE, (1): Enable LPI2C peripheral
Offset: 2b, Width: 6b, N/A
Offset: 2b, Width: 6b, N/A
Offset: 0x00000011, Width: 8b; If not 0xFF, used as the 7-bit I2C slave address
Offset: 0x00000011, Width: 8b; If not 0xFF, used as the 7-bit I2C slave address
Offset: 0x00000012, Width: 16b; Timeout in milliseconds for active peripheral detection
Offset: 0x00000012, Width: 16b; Timeout in milliseconds for active peripheral detection
Offset: 0x0000001E, Width: 8b; One's complement of direct boot flag. 0xFE represents direct boot
Offset: 0b, Width: 1b, Enable direct boot
- ENABLE, (0): Enable direct boot
- DISABLE, (1): Disable direct boot - standard boot with ISP
Offset: 1b, Width: 7b, N/A
Offset: 1b, Width: 7b, N/A
Offset: 0b, Width: 1b, Enable direct boot
- ENABLE, (0): Enable direct boot
- DISABLE, (1): Disable direct boot - standard boot with ISP
Offset: 1b, Width: 7b, N/A
Offset: 1b, Width: 7b, N/A
Offset: 0x0000001E, Width: 8b; One's complement of direct boot flag. 0xFE represents direct boot
Offset: 0b, Width: 1b, Enable direct boot
- ENABLE, (0): Enable direct boot
- DISABLE, (1): Disable direct boot - standard boot with ISP
Offset: 1b, Width: 7b, N/A
Offset: 1b, Width: 7b, N/A
Offset: 0b, Width: 1b, Enable direct boot
- ENABLE, (0): Enable direct boot
- DISABLE, (1): Disable direct boot - standard boot with ISP
Offset: 1b, Width: 7b, N/A
Offset: 1b, Width: 7b, N/A
Offset: 0x00000020, Width: 32b; The information about total size of the image
Offset: 0x00000020, Width: 32b; The information about total size of the image
Offset: 0x00000024, Width: 32b; Firmware version, stored in little endian format. Used for anti-rollback protection. New firmware must have the same or higher FW version
Offset: 0x00000024, Width: 32b; Firmware version, stored in little endian format. Used for anti-rollback protection. New firmware must have the same or higher FW version
Path to BCA configuration or binary file
Offset: 0x00000000, Width: 64b; Backdoor Comparison Key. Refer to Verify Backdoor Access Key Command and Unsecuring the Chip Using Backdoor Key Access.
Offset: 0x00000000, Width: 64b; Backdoor Comparison Key. Refer to Verify Backdoor Access Key Command and Unsecuring the Chip Using Backdoor Key Access.
Offset: 0x00000008, Width: 32b; Program flash protection bytes. Refer to the description of the Program Flash Protection Registers (FPROT0-3).
Offset: 0b, Width: 8b, Program Flash Protection Registers (FPROT3)
Offset: 8b, Width: 8b, Program Flash Protection Registers (FPROT2)
Offset: 16b, Width: 8b, Program Flash Protection Registers (FPROT1)
Offset: 24b, Width: 8b, Program Flash Protection Registers (FPROT0)
Offset: 0b, Width: 8b, Program Flash Protection Registers (FPROT3)
Offset: 8b, Width: 8b, Program Flash Protection Registers (FPROT2)
Offset: 16b, Width: 8b, Program Flash Protection Registers (FPROT1)
Offset: 24b, Width: 8b, Program Flash Protection Registers (FPROT0)
Offset: 0x00000008, Width: 32b; Program flash protection bytes. Refer to the description of the Program Flash Protection Registers (FPROT0-3).
Offset: 0b, Width: 8b, Program Flash Protection Registers (FPROT3)
Offset: 8b, Width: 8b, Program Flash Protection Registers (FPROT2)
Offset: 16b, Width: 8b, Program Flash Protection Registers (FPROT1)
Offset: 24b, Width: 8b, Program Flash Protection Registers (FPROT0)
Offset: 0b, Width: 8b, Program Flash Protection Registers (FPROT3)
Offset: 8b, Width: 8b, Program Flash Protection Registers (FPROT2)
Offset: 16b, Width: 8b, Program Flash Protection Registers (FPROT1)
Offset: 24b, Width: 8b, Program Flash Protection Registers (FPROT0)
Offset: 0x0000000C, Width: 8b; DSA Secure Lifecycle state
Offset: 0b, Width: 8b, DSA Secure Lifecycle state
- OEMOPENROP0, (254): Most permissive state - full ISP command set available in all conditions
- OEMCLOSEDROP1, (144): Moderate security - partial ISP commands on normal boot, full commands via ROMAPI
- OEMCLOSEDROP2, (149): Higher security - no ISP commands on normal boot, partial commands via ROMAPI or invalid image
- OEMCLOSEDROP3, (155): Very high security - no ISP commands except ReceiveSBFile via ROMAPI for secure devices only
- OEMCLOSEDNORETURN, (107): Maximum security - no ISP commands available in any condition, device cannot be reprogrammed
Offset: 0b, Width: 8b, DSA Secure Lifecycle state
- OEMOPENROP0, (254): Most permissive state - full ISP command set available in all conditions
- OEMCLOSEDROP1, (144): Moderate security - partial ISP commands on normal boot, full commands via ROMAPI
- OEMCLOSEDROP2, (149): Higher security - no ISP commands on normal boot, partial commands via ROMAPI or invalid image
- OEMCLOSEDROP3, (155): Very high security - no ISP commands except ReceiveSBFile via ROMAPI for secure devices only
- OEMCLOSEDNORETURN, (107): Maximum security - no ISP commands available in any condition, device cannot be reprogrammed
Offset: 0x0000000C, Width: 8b; DSA Secure Lifecycle state
Offset: 0b, Width: 8b, DSA Secure Lifecycle state
- OEMOPENROP0, (254): Most permissive state - full ISP command set available in all conditions
- OEMCLOSEDROP1, (144): Moderate security - partial ISP commands on normal boot, full commands via ROMAPI
- OEMCLOSEDROP2, (149): Higher security - no ISP commands on normal boot, partial commands via ROMAPI or invalid image
- OEMCLOSEDROP3, (155): Very high security - no ISP commands except ReceiveSBFile via ROMAPI for secure devices only
- OEMCLOSEDNORETURN, (107): Maximum security - no ISP commands available in any condition, device cannot be reprogrammed
Offset: 0b, Width: 8b, DSA Secure Lifecycle state
- OEMOPENROP0, (254): Most permissive state - full ISP command set available in all conditions
- OEMCLOSEDROP1, (144): Moderate security - partial ISP commands on normal boot, full commands via ROMAPI
- OEMCLOSEDROP2, (149): Higher security - no ISP commands on normal boot, partial commands via ROMAPI or invalid image
- OEMCLOSEDROP3, (155): Very high security - no ISP commands except ReceiveSBFile via ROMAPI for secure devices only
- OEMCLOSEDNORETURN, (107): Maximum security - no ISP commands available in any condition, device cannot be reprogrammed
Offset: 0x0000000D, Width: 8b; Flash nonvolatile option byte. Refer to the description of the Flash Option Register (FOPT).
Offset: 0b, Width: 1b, Controls which power mode register takes effect
- SIMPWRMODE, (1): Writing SIMPWRMODE register takes effect, writing SIMPWR register doesn't take effect
- SIMPWR, (0): Writing SIMPWRMODE register doesn't take effect, writing SIMPWR register takes effect
Offset: 1b, Width: 7b, N/A
Offset: 1b, Width: 7b, N/A
Offset: 0b, Width: 1b, Controls which power mode register takes effect
- SIMPWRMODE, (1): Writing SIMPWRMODE register takes effect, writing SIMPWR register doesn't take effect
- SIMPWR, (0): Writing SIMPWRMODE register doesn't take effect, writing SIMPWR register takes effect
Offset: 1b, Width: 7b, N/A
Offset: 1b, Width: 7b, N/A
Offset: 0x0000000D, Width: 8b; Flash nonvolatile option byte. Refer to the description of the Flash Option Register (FOPT).
Offset: 0b, Width: 1b, Controls which power mode register takes effect
- SIMPWRMODE, (1): Writing SIMPWRMODE register takes effect, writing SIMPWR register doesn't take effect
- SIMPWR, (0): Writing SIMPWRMODE register doesn't take effect, writing SIMPWR register takes effect
Offset: 1b, Width: 7b, N/A
Offset: 1b, Width: 7b, N/A
Offset: 0b, Width: 1b, Controls which power mode register takes effect
- SIMPWRMODE, (1): Writing SIMPWRMODE register takes effect, writing SIMPWR register doesn't take effect
- SIMPWR, (0): Writing SIMPWRMODE register doesn't take effect, writing SIMPWR register takes effect
Offset: 1b, Width: 7b, N/A
Offset: 1b, Width: 7b, N/A
Path to FCF configuration or binary file