Flash Configuration Field settings. Default values are always loaded from application first.
FCF can be provided in one of three ways:
1. As a nested dictionary under the 'fcf' key - copy values directly from the FCF.YAML template
2. As a path to a YAML file containing FCF configuration - use 'fcf: path/to/fcf.yaml'
3. As a path to a binary FCF file - use 'fcf: path/to/fcf.bin'
If any FCF configuration is provided, it will update the application values accordingly. The binary option completely replaces the FCF content, while the YAML and dictionary options selectively update FCF register values.
NXP chip family identifier.
Revision of silicon. The 'latest' name, means most current revision.
Definition if application is Execute in Place(XiP) or loaded to RAM during reset sequence.
Specification of final master boot image authentication.
The path for result binary file.
The input application image to by modified to Master Boot Image.
Offset: 0x00000000, Width: 64b; Backdoor Comparison Key. Refer to Verify Backdoor Access Key Command and Unsecuring the Chip Using Backdoor Key Access.
Offset: 0x00000000, Width: 64b; Backdoor Comparison Key. Refer to Verify Backdoor Access Key Command and Unsecuring the Chip Using Backdoor Key Access.
Offset: 0x00000008, Width: 32b; Program flash protection bytes. Refer to the description of the Program Flash Protection Registers (FPROT0-3).
Offset: 0b, Width: 8b, Program Flash Protection Registers (FPROT3)
Offset: 8b, Width: 8b, Program Flash Protection Registers (FPROT2)
Offset: 16b, Width: 8b, Program Flash Protection Registers (FPROT1)
Offset: 24b, Width: 8b, Program Flash Protection Registers (FPROT0)
Offset: 0b, Width: 8b, Program Flash Protection Registers (FPROT3)
Offset: 8b, Width: 8b, Program Flash Protection Registers (FPROT2)
Offset: 16b, Width: 8b, Program Flash Protection Registers (FPROT1)
Offset: 24b, Width: 8b, Program Flash Protection Registers (FPROT0)
Offset: 0x00000008, Width: 32b; Program flash protection bytes. Refer to the description of the Program Flash Protection Registers (FPROT0-3).
Offset: 0b, Width: 8b, Program Flash Protection Registers (FPROT3)
Offset: 8b, Width: 8b, Program Flash Protection Registers (FPROT2)
Offset: 16b, Width: 8b, Program Flash Protection Registers (FPROT1)
Offset: 24b, Width: 8b, Program Flash Protection Registers (FPROT0)
Offset: 0b, Width: 8b, Program Flash Protection Registers (FPROT3)
Offset: 8b, Width: 8b, Program Flash Protection Registers (FPROT2)
Offset: 16b, Width: 8b, Program Flash Protection Registers (FPROT1)
Offset: 24b, Width: 8b, Program Flash Protection Registers (FPROT0)
Offset: 0x0000000C, Width: 8b; Flash security byte. Refer to the description of the Flash Security Register (FSEC).
Offset: 0b, Width: 2b, Flash Security.
- SECURE0, (0): MCU security status is secure.
- SECURE, (1): MCU security status is secure.
- UNSECURE, (2): MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)
- SECURE3, (3): MCU security status is secure.
Offset: 6b, Width: 2b, Backdoor Key Security Enable. Enables or disables backdoor key access to the flash memory module.
- DISABLED0, (0): Backdoor key access disabled
- DISABLED, (1): Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
- ENABLED, (2): Backdoor key access enabled
- DISABLED3, (3): Backdoor key access disabled
Offset: 0b, Width: 2b, Flash Security.
- SECURE0, (0): MCU security status is secure.
- SECURE, (1): MCU security status is secure.
- UNSECURE, (2): MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)
- SECURE3, (3): MCU security status is secure.
Offset: 6b, Width: 2b, Backdoor Key Security Enable. Enables or disables backdoor key access to the flash memory module.
- DISABLED0, (0): Backdoor key access disabled
- DISABLED, (1): Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
- ENABLED, (2): Backdoor key access enabled
- DISABLED3, (3): Backdoor key access disabled
Offset: 0x0000000C, Width: 8b; Flash security byte. Refer to the description of the Flash Security Register (FSEC).
Offset: 0b, Width: 2b, Flash Security.
- SECURE0, (0): MCU security status is secure.
- SECURE, (1): MCU security status is secure.
- UNSECURE, (2): MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)
- SECURE3, (3): MCU security status is secure.
Offset: 6b, Width: 2b, Backdoor Key Security Enable. Enables or disables backdoor key access to the flash memory module.
- DISABLED0, (0): Backdoor key access disabled
- DISABLED, (1): Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
- ENABLED, (2): Backdoor key access enabled
- DISABLED3, (3): Backdoor key access disabled
Offset: 0b, Width: 2b, Flash Security.
- SECURE0, (0): MCU security status is secure.
- SECURE, (1): MCU security status is secure.
- UNSECURE, (2): MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)
- SECURE3, (3): MCU security status is secure.
Offset: 6b, Width: 2b, Backdoor Key Security Enable. Enables or disables backdoor key access to the flash memory module.
- DISABLED0, (0): Backdoor key access disabled
- DISABLED, (1): Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
- ENABLED, (2): Backdoor key access enabled
- DISABLED3, (3): Backdoor key access disabled
Offset: 0x0000000D, Width: 8b; Flash nonvolatile option byte. Refer to the description of the Flash Option Register (FOPT).
Offset: 0b, Width: 1b, Controls the reset value of clock divider of IRC 48 Mhz to feed the Core and platform clocks. Larger divide value selections produce lower average power consumption during POR and reset sequencing and after reset exit.
- DIVBY2, (0): Core and system clock divider (OUTDIV1) is 0x1 (divide by 2).
- DIVBY1, (1): Core and system clock divider (OUTDIV1) is 0x0 (divide by 1).
Offset: 1b, Width: 1b, N/A
Offset: 1b, Width: 1b, N/A
Offset: 2b, Width: 1b, Enables/disables control for the NMI function.
- DISABLE, (0): NMI interrupts are always blocked. The associated pin continues to default to NMIb pin controls with internal pullup enabled. When NMIb pin function is disabled, it cannot be used as a source for low-power mode wake-up. If the NMI function is not required, either for an interrupt or wake up source, it is recommended that the NMI function be disabled by writing 0 to NMIPINCFG.
- ENABLE, (1): NMI_b pin/interrupts reset default to enabled.
Offset: 3b, Width: 1b, Enables/disables control for the RESET pin.
- DISABLE, (0): RESETB pin is disabled following a POR and cannot be enabled as reset function. When this option is selected, there could be a short period of contention during a POR ramp where the MCU drives the pin low prior to establishing the setting of this option and releasing the reset function on the pin. This bit is preserved through system resets and low-power modes. When RESETB pin function is disabled, it cannot be used as a source for low-power mode wake-up.
- ENABLE, (1): The port is configured with pullup enabled, passive filter enabled.
Offset: 4b, Width: 1b, N/A
Offset: 4b, Width: 1b, N/A
Offset: 5b, Width: 1b, N/A
Offset: 5b, Width: 1b, N/A
Offset: 6b, Width: 2b, N/A
Offset: 6b, Width: 2b, N/A
Offset: 0b, Width: 1b, Controls the reset value of clock divider of IRC 48 Mhz to feed the Core and platform clocks. Larger divide value selections produce lower average power consumption during POR and reset sequencing and after reset exit.
- DIVBY2, (0): Core and system clock divider (OUTDIV1) is 0x1 (divide by 2).
- DIVBY1, (1): Core and system clock divider (OUTDIV1) is 0x0 (divide by 1).
Offset: 1b, Width: 1b, N/A
Offset: 1b, Width: 1b, N/A
Offset: 2b, Width: 1b, Enables/disables control for the NMI function.
- DISABLE, (0): NMI interrupts are always blocked. The associated pin continues to default to NMIb pin controls with internal pullup enabled. When NMIb pin function is disabled, it cannot be used as a source for low-power mode wake-up. If the NMI function is not required, either for an interrupt or wake up source, it is recommended that the NMI function be disabled by writing 0 to NMIPINCFG.
- ENABLE, (1): NMI_b pin/interrupts reset default to enabled.
Offset: 3b, Width: 1b, Enables/disables control for the RESET pin.
- DISABLE, (0): RESETB pin is disabled following a POR and cannot be enabled as reset function. When this option is selected, there could be a short period of contention during a POR ramp where the MCU drives the pin low prior to establishing the setting of this option and releasing the reset function on the pin. This bit is preserved through system resets and low-power modes. When RESETB pin function is disabled, it cannot be used as a source for low-power mode wake-up.
- ENABLE, (1): The port is configured with pullup enabled, passive filter enabled.
Offset: 4b, Width: 1b, N/A
Offset: 4b, Width: 1b, N/A
Offset: 5b, Width: 1b, N/A
Offset: 5b, Width: 1b, N/A
Offset: 6b, Width: 2b, N/A
Offset: 6b, Width: 2b, N/A
Offset: 0x0000000D, Width: 8b; Flash nonvolatile option byte. Refer to the description of the Flash Option Register (FOPT).
Offset: 0b, Width: 1b, Controls the reset value of clock divider of IRC 48 Mhz to feed the Core and platform clocks. Larger divide value selections produce lower average power consumption during POR and reset sequencing and after reset exit.
- DIVBY2, (0): Core and system clock divider (OUTDIV1) is 0x1 (divide by 2).
- DIVBY1, (1): Core and system clock divider (OUTDIV1) is 0x0 (divide by 1).
Offset: 1b, Width: 1b, N/A
Offset: 1b, Width: 1b, N/A
Offset: 2b, Width: 1b, Enables/disables control for the NMI function.
- DISABLE, (0): NMI interrupts are always blocked. The associated pin continues to default to NMIb pin controls with internal pullup enabled. When NMIb pin function is disabled, it cannot be used as a source for low-power mode wake-up. If the NMI function is not required, either for an interrupt or wake up source, it is recommended that the NMI function be disabled by writing 0 to NMIPINCFG.
- ENABLE, (1): NMI_b pin/interrupts reset default to enabled.
Offset: 3b, Width: 1b, Enables/disables control for the RESET pin.
- DISABLE, (0): RESETB pin is disabled following a POR and cannot be enabled as reset function. When this option is selected, there could be a short period of contention during a POR ramp where the MCU drives the pin low prior to establishing the setting of this option and releasing the reset function on the pin. This bit is preserved through system resets and low-power modes. When RESETB pin function is disabled, it cannot be used as a source for low-power mode wake-up.
- ENABLE, (1): The port is configured with pullup enabled, passive filter enabled.
Offset: 4b, Width: 1b, N/A
Offset: 4b, Width: 1b, N/A
Offset: 5b, Width: 1b, N/A
Offset: 5b, Width: 1b, N/A
Offset: 6b, Width: 2b, N/A
Offset: 6b, Width: 2b, N/A
Offset: 0b, Width: 1b, Controls the reset value of clock divider of IRC 48 Mhz to feed the Core and platform clocks. Larger divide value selections produce lower average power consumption during POR and reset sequencing and after reset exit.
- DIVBY2, (0): Core and system clock divider (OUTDIV1) is 0x1 (divide by 2).
- DIVBY1, (1): Core and system clock divider (OUTDIV1) is 0x0 (divide by 1).
Offset: 1b, Width: 1b, N/A
Offset: 1b, Width: 1b, N/A
Offset: 2b, Width: 1b, Enables/disables control for the NMI function.
- DISABLE, (0): NMI interrupts are always blocked. The associated pin continues to default to NMIb pin controls with internal pullup enabled. When NMIb pin function is disabled, it cannot be used as a source for low-power mode wake-up. If the NMI function is not required, either for an interrupt or wake up source, it is recommended that the NMI function be disabled by writing 0 to NMIPINCFG.
- ENABLE, (1): NMI_b pin/interrupts reset default to enabled.
Offset: 3b, Width: 1b, Enables/disables control for the RESET pin.
- DISABLE, (0): RESETB pin is disabled following a POR and cannot be enabled as reset function. When this option is selected, there could be a short period of contention during a POR ramp where the MCU drives the pin low prior to establishing the setting of this option and releasing the reset function on the pin. This bit is preserved through system resets and low-power modes. When RESETB pin function is disabled, it cannot be used as a source for low-power mode wake-up.
- ENABLE, (1): The port is configured with pullup enabled, passive filter enabled.
Offset: 4b, Width: 1b, N/A
Offset: 4b, Width: 1b, N/A
Offset: 5b, Width: 1b, N/A
Offset: 5b, Width: 1b, N/A
Offset: 6b, Width: 2b, N/A
Offset: 6b, Width: 2b, N/A
Offset: 0x0000000E, Width: 8b; EEPROM Region Protect. Individual emulated EEPROM regions can be protected from alteration by setting the associated EPROT bit to the protected state. The EPROT bits are not used when the FlexNVM Partition Code is set to data flash only. When the FlexNVM Partition Code is set to data flash and EEPROM or EEPROM only, each EPROT bit covers one-eighth of the configured EEPROM data. In NVM Normal mode: The protection can only be increased, meaning currently-unprotected memory can be protected, but currently-protected memory cannot be unprotected. Unprotected regions are marked with a 1 and protected regions use a 0. Trying to alter data by writing to any protected area in the emulated EEPROM results in a protection violation error and sets the FSTAT[FPVIOL] bit.
Offset: 0b, Width: 1b, EEPROM Region Protect Bit 0 - Controls protection for 1/8th of the EEPROM data (first region)
- PROTECTED, (0): EEPROM region 0 is protected
- UNPROTECTED, (1): EEPROM region 0 is not protected
Offset: 1b, Width: 1b, EEPROM Region Protect Bit 1 - Controls protection for 1/8th of the EEPROM data (second region)
- PROTECTED, (0): EEPROM region 1 is protected
- UNPROTECTED, (1): EEPROM region 1 is not protected
Offset: 2b, Width: 1b, EEPROM Region Protect Bit 2 - Controls protection for 1/8th of the EEPROM data (third region)
- PROTECTED, (0): EEPROM region 2 is protected
- UNPROTECTED, (1): EEPROM region 2 is not protected
Offset: 3b, Width: 1b, EEPROM Region Protect Bit 3 - Controls protection for 1/8th of the EEPROM data (fourth region)
- PROTECTED, (0): EEPROM region 3 is protected
- UNPROTECTED, (1): EEPROM region 3 is not protected
Offset: 4b, Width: 1b, EEPROM Region Protect Bit 4 - Controls protection for 1/8th of the EEPROM data (fifth region)
- PROTECTED, (0): EEPROM region 4 is protected
- UNPROTECTED, (1): EEPROM region 4 is not protected
Offset: 5b, Width: 1b, EEPROM Region Protect Bit 5 - Controls protection for 1/8th of the EEPROM data (sixth region)
- PROTECTED, (0): EEPROM region 5 is protected
- UNPROTECTED, (1): EEPROM region 5 is not protected
Offset: 6b, Width: 1b, EEPROM Region Protect Bit 6 - Controls protection for 1/8th of the EEPROM data (seventh region)
- PROTECTED, (0): EEPROM region 6 is protected
- UNPROTECTED, (1): EEPROM region 6 is not protected
Offset: 7b, Width: 1b, EEPROM Region Protect Bit 7 - Controls protection for 1/8th of the EEPROM data (eighth region)
- PROTECTED, (0): EEPROM region 7 is protected
- UNPROTECTED, (1): EEPROM region 7 is not protected
Offset: 0b, Width: 1b, EEPROM Region Protect Bit 0 - Controls protection for 1/8th of the EEPROM data (first region)
- PROTECTED, (0): EEPROM region 0 is protected
- UNPROTECTED, (1): EEPROM region 0 is not protected
Offset: 1b, Width: 1b, EEPROM Region Protect Bit 1 - Controls protection for 1/8th of the EEPROM data (second region)
- PROTECTED, (0): EEPROM region 1 is protected
- UNPROTECTED, (1): EEPROM region 1 is not protected
Offset: 2b, Width: 1b, EEPROM Region Protect Bit 2 - Controls protection for 1/8th of the EEPROM data (third region)
- PROTECTED, (0): EEPROM region 2 is protected
- UNPROTECTED, (1): EEPROM region 2 is not protected
Offset: 3b, Width: 1b, EEPROM Region Protect Bit 3 - Controls protection for 1/8th of the EEPROM data (fourth region)
- PROTECTED, (0): EEPROM region 3 is protected
- UNPROTECTED, (1): EEPROM region 3 is not protected
Offset: 4b, Width: 1b, EEPROM Region Protect Bit 4 - Controls protection for 1/8th of the EEPROM data (fifth region)
- PROTECTED, (0): EEPROM region 4 is protected
- UNPROTECTED, (1): EEPROM region 4 is not protected
Offset: 5b, Width: 1b, EEPROM Region Protect Bit 5 - Controls protection for 1/8th of the EEPROM data (sixth region)
- PROTECTED, (0): EEPROM region 5 is protected
- UNPROTECTED, (1): EEPROM region 5 is not protected
Offset: 6b, Width: 1b, EEPROM Region Protect Bit 6 - Controls protection for 1/8th of the EEPROM data (seventh region)
- PROTECTED, (0): EEPROM region 6 is protected
- UNPROTECTED, (1): EEPROM region 6 is not protected
Offset: 7b, Width: 1b, EEPROM Region Protect Bit 7 - Controls protection for 1/8th of the EEPROM data (eighth region)
- PROTECTED, (0): EEPROM region 7 is protected
- UNPROTECTED, (1): EEPROM region 7 is not protected
Offset: 0x0000000E, Width: 8b; EEPROM Region Protect. Individual emulated EEPROM regions can be protected from alteration by setting the associated EPROT bit to the protected state. The EPROT bits are not used when the FlexNVM Partition Code is set to data flash only. When the FlexNVM Partition Code is set to data flash and EEPROM or EEPROM only, each EPROT bit covers one-eighth of the configured EEPROM data. In NVM Normal mode: The protection can only be increased, meaning currently-unprotected memory can be protected, but currently-protected memory cannot be unprotected. Unprotected regions are marked with a 1 and protected regions use a 0. Trying to alter data by writing to any protected area in the emulated EEPROM results in a protection violation error and sets the FSTAT[FPVIOL] bit.
Offset: 0b, Width: 1b, EEPROM Region Protect Bit 0 - Controls protection for 1/8th of the EEPROM data (first region)
- PROTECTED, (0): EEPROM region 0 is protected
- UNPROTECTED, (1): EEPROM region 0 is not protected
Offset: 1b, Width: 1b, EEPROM Region Protect Bit 1 - Controls protection for 1/8th of the EEPROM data (second region)
- PROTECTED, (0): EEPROM region 1 is protected
- UNPROTECTED, (1): EEPROM region 1 is not protected
Offset: 2b, Width: 1b, EEPROM Region Protect Bit 2 - Controls protection for 1/8th of the EEPROM data (third region)
- PROTECTED, (0): EEPROM region 2 is protected
- UNPROTECTED, (1): EEPROM region 2 is not protected
Offset: 3b, Width: 1b, EEPROM Region Protect Bit 3 - Controls protection for 1/8th of the EEPROM data (fourth region)
- PROTECTED, (0): EEPROM region 3 is protected
- UNPROTECTED, (1): EEPROM region 3 is not protected
Offset: 4b, Width: 1b, EEPROM Region Protect Bit 4 - Controls protection for 1/8th of the EEPROM data (fifth region)
- PROTECTED, (0): EEPROM region 4 is protected
- UNPROTECTED, (1): EEPROM region 4 is not protected
Offset: 5b, Width: 1b, EEPROM Region Protect Bit 5 - Controls protection for 1/8th of the EEPROM data (sixth region)
- PROTECTED, (0): EEPROM region 5 is protected
- UNPROTECTED, (1): EEPROM region 5 is not protected
Offset: 6b, Width: 1b, EEPROM Region Protect Bit 6 - Controls protection for 1/8th of the EEPROM data (seventh region)
- PROTECTED, (0): EEPROM region 6 is protected
- UNPROTECTED, (1): EEPROM region 6 is not protected
Offset: 7b, Width: 1b, EEPROM Region Protect Bit 7 - Controls protection for 1/8th of the EEPROM data (eighth region)
- PROTECTED, (0): EEPROM region 7 is protected
- UNPROTECTED, (1): EEPROM region 7 is not protected
Offset: 0b, Width: 1b, EEPROM Region Protect Bit 0 - Controls protection for 1/8th of the EEPROM data (first region)
- PROTECTED, (0): EEPROM region 0 is protected
- UNPROTECTED, (1): EEPROM region 0 is not protected
Offset: 1b, Width: 1b, EEPROM Region Protect Bit 1 - Controls protection for 1/8th of the EEPROM data (second region)
- PROTECTED, (0): EEPROM region 1 is protected
- UNPROTECTED, (1): EEPROM region 1 is not protected
Offset: 2b, Width: 1b, EEPROM Region Protect Bit 2 - Controls protection for 1/8th of the EEPROM data (third region)
- PROTECTED, (0): EEPROM region 2 is protected
- UNPROTECTED, (1): EEPROM region 2 is not protected
Offset: 3b, Width: 1b, EEPROM Region Protect Bit 3 - Controls protection for 1/8th of the EEPROM data (fourth region)
- PROTECTED, (0): EEPROM region 3 is protected
- UNPROTECTED, (1): EEPROM region 3 is not protected
Offset: 4b, Width: 1b, EEPROM Region Protect Bit 4 - Controls protection for 1/8th of the EEPROM data (fifth region)
- PROTECTED, (0): EEPROM region 4 is protected
- UNPROTECTED, (1): EEPROM region 4 is not protected
Offset: 5b, Width: 1b, EEPROM Region Protect Bit 5 - Controls protection for 1/8th of the EEPROM data (sixth region)
- PROTECTED, (0): EEPROM region 5 is protected
- UNPROTECTED, (1): EEPROM region 5 is not protected
Offset: 6b, Width: 1b, EEPROM Region Protect Bit 6 - Controls protection for 1/8th of the EEPROM data (seventh region)
- PROTECTED, (0): EEPROM region 6 is protected
- UNPROTECTED, (1): EEPROM region 6 is not protected
Offset: 7b, Width: 1b, EEPROM Region Protect Bit 7 - Controls protection for 1/8th of the EEPROM data (eighth region)
- PROTECTED, (0): EEPROM region 7 is protected
- UNPROTECTED, (1): EEPROM region 7 is not protected
Offset: 0x0000000F, Width: 8b; Data Flash Region Protect. Individual data flash regions can be protected from program and erase operations by setting the associated DPROT bit to the protected state. Each DPROT bit protects one-eighth of the partitioned data flash memory space. The granularity of data flash protection cannot be less than the data flash sector size. If an unused DPROT bit is set to the protected state, the Erase all Blocks command does not execute and sets the FSTAT[FPVIOL] bit. Unprotected regions are marked with a 1 and protected regions use a 0. Trying to alter data in any protected area in the data flash memory results in a protection violation error and sets the FSTAT[FPVIOL] bit.
Offset: 0b, Width: 1b, Data Flash Region Protect Bit 0 - Controls protection for 1/8th of the data flash (first region)
- PROTECTED, (0): Data Flash region 0 is protected
- UNPROTECTED, (1): Data Flash region 0 is not protected
Offset: 1b, Width: 1b, Data Flash Region Protect Bit 1 - Controls protection for 1/8th of the data flash (second region)
- PROTECTED, (0): Data Flash region 1 is protected
- UNPROTECTED, (1): Data Flash region 1 is not protected
Offset: 2b, Width: 1b, Data Flash Region Protect Bit 2 - Controls protection for 1/8th of the data flash (third region)
- PROTECTED, (0): Data Flash region 2 is protected
- UNPROTECTED, (1): Data Flash region 2 is not protected
Offset: 3b, Width: 1b, Data Flash Region Protect Bit 3 - Controls protection for 1/8th of the data flash (fourth region)
- PROTECTED, (0): Data Flash region 3 is protected
- UNPROTECTED, (1): Data Flash region 3 is not protected
Offset: 4b, Width: 1b, Data Flash Region Protect Bit 4 - Controls protection for 1/8th of the data flash (fifth region)
- PROTECTED, (0): Data Flash region 4 is protected
- UNPROTECTED, (1): Data Flash region 4 is not protected
Offset: 5b, Width: 1b, Data Flash Region Protect Bit 5 - Controls protection for 1/8th of the data flash (sixth region)
- PROTECTED, (0): Data Flash region 5 is protected
- UNPROTECTED, (1): Data Flash region 5 is not protected
Offset: 6b, Width: 1b, Data Flash Region Protect Bit 6 - Controls protection for 1/8th of the data flash (seventh region)
- PROTECTED, (0): Data Flash region 6 is protected
- UNPROTECTED, (1): Data Flash region 6 is not protected
Offset: 7b, Width: 1b, Data Flash Region Protect Bit 7 - Controls protection for 1/8th of the data flash (eighth region)
- PROTECTED, (0): Data Flash region 7 is protected
- UNPROTECTED, (1): Data Flash region 7 is not protected
Offset: 0b, Width: 1b, Data Flash Region Protect Bit 0 - Controls protection for 1/8th of the data flash (first region)
- PROTECTED, (0): Data Flash region 0 is protected
- UNPROTECTED, (1): Data Flash region 0 is not protected
Offset: 1b, Width: 1b, Data Flash Region Protect Bit 1 - Controls protection for 1/8th of the data flash (second region)
- PROTECTED, (0): Data Flash region 1 is protected
- UNPROTECTED, (1): Data Flash region 1 is not protected
Offset: 2b, Width: 1b, Data Flash Region Protect Bit 2 - Controls protection for 1/8th of the data flash (third region)
- PROTECTED, (0): Data Flash region 2 is protected
- UNPROTECTED, (1): Data Flash region 2 is not protected
Offset: 3b, Width: 1b, Data Flash Region Protect Bit 3 - Controls protection for 1/8th of the data flash (fourth region)
- PROTECTED, (0): Data Flash region 3 is protected
- UNPROTECTED, (1): Data Flash region 3 is not protected
Offset: 4b, Width: 1b, Data Flash Region Protect Bit 4 - Controls protection for 1/8th of the data flash (fifth region)
- PROTECTED, (0): Data Flash region 4 is protected
- UNPROTECTED, (1): Data Flash region 4 is not protected
Offset: 5b, Width: 1b, Data Flash Region Protect Bit 5 - Controls protection for 1/8th of the data flash (sixth region)
- PROTECTED, (0): Data Flash region 5 is protected
- UNPROTECTED, (1): Data Flash region 5 is not protected
Offset: 6b, Width: 1b, Data Flash Region Protect Bit 6 - Controls protection for 1/8th of the data flash (seventh region)
- PROTECTED, (0): Data Flash region 6 is protected
- UNPROTECTED, (1): Data Flash region 6 is not protected
Offset: 7b, Width: 1b, Data Flash Region Protect Bit 7 - Controls protection for 1/8th of the data flash (eighth region)
- PROTECTED, (0): Data Flash region 7 is protected
- UNPROTECTED, (1): Data Flash region 7 is not protected
Offset: 0x0000000F, Width: 8b; Data Flash Region Protect. Individual data flash regions can be protected from program and erase operations by setting the associated DPROT bit to the protected state. Each DPROT bit protects one-eighth of the partitioned data flash memory space. The granularity of data flash protection cannot be less than the data flash sector size. If an unused DPROT bit is set to the protected state, the Erase all Blocks command does not execute and sets the FSTAT[FPVIOL] bit. Unprotected regions are marked with a 1 and protected regions use a 0. Trying to alter data in any protected area in the data flash memory results in a protection violation error and sets the FSTAT[FPVIOL] bit.
Offset: 0b, Width: 1b, Data Flash Region Protect Bit 0 - Controls protection for 1/8th of the data flash (first region)
- PROTECTED, (0): Data Flash region 0 is protected
- UNPROTECTED, (1): Data Flash region 0 is not protected
Offset: 1b, Width: 1b, Data Flash Region Protect Bit 1 - Controls protection for 1/8th of the data flash (second region)
- PROTECTED, (0): Data Flash region 1 is protected
- UNPROTECTED, (1): Data Flash region 1 is not protected
Offset: 2b, Width: 1b, Data Flash Region Protect Bit 2 - Controls protection for 1/8th of the data flash (third region)
- PROTECTED, (0): Data Flash region 2 is protected
- UNPROTECTED, (1): Data Flash region 2 is not protected
Offset: 3b, Width: 1b, Data Flash Region Protect Bit 3 - Controls protection for 1/8th of the data flash (fourth region)
- PROTECTED, (0): Data Flash region 3 is protected
- UNPROTECTED, (1): Data Flash region 3 is not protected
Offset: 4b, Width: 1b, Data Flash Region Protect Bit 4 - Controls protection for 1/8th of the data flash (fifth region)
- PROTECTED, (0): Data Flash region 4 is protected
- UNPROTECTED, (1): Data Flash region 4 is not protected
Offset: 5b, Width: 1b, Data Flash Region Protect Bit 5 - Controls protection for 1/8th of the data flash (sixth region)
- PROTECTED, (0): Data Flash region 5 is protected
- UNPROTECTED, (1): Data Flash region 5 is not protected
Offset: 6b, Width: 1b, Data Flash Region Protect Bit 6 - Controls protection for 1/8th of the data flash (seventh region)
- PROTECTED, (0): Data Flash region 6 is protected
- UNPROTECTED, (1): Data Flash region 6 is not protected
Offset: 7b, Width: 1b, Data Flash Region Protect Bit 7 - Controls protection for 1/8th of the data flash (eighth region)
- PROTECTED, (0): Data Flash region 7 is protected
- UNPROTECTED, (1): Data Flash region 7 is not protected
Offset: 0b, Width: 1b, Data Flash Region Protect Bit 0 - Controls protection for 1/8th of the data flash (first region)
- PROTECTED, (0): Data Flash region 0 is protected
- UNPROTECTED, (1): Data Flash region 0 is not protected
Offset: 1b, Width: 1b, Data Flash Region Protect Bit 1 - Controls protection for 1/8th of the data flash (second region)
- PROTECTED, (0): Data Flash region 1 is protected
- UNPROTECTED, (1): Data Flash region 1 is not protected
Offset: 2b, Width: 1b, Data Flash Region Protect Bit 2 - Controls protection for 1/8th of the data flash (third region)
- PROTECTED, (0): Data Flash region 2 is protected
- UNPROTECTED, (1): Data Flash region 2 is not protected
Offset: 3b, Width: 1b, Data Flash Region Protect Bit 3 - Controls protection for 1/8th of the data flash (fourth region)
- PROTECTED, (0): Data Flash region 3 is protected
- UNPROTECTED, (1): Data Flash region 3 is not protected
Offset: 4b, Width: 1b, Data Flash Region Protect Bit 4 - Controls protection for 1/8th of the data flash (fifth region)
- PROTECTED, (0): Data Flash region 4 is protected
- UNPROTECTED, (1): Data Flash region 4 is not protected
Offset: 5b, Width: 1b, Data Flash Region Protect Bit 5 - Controls protection for 1/8th of the data flash (sixth region)
- PROTECTED, (0): Data Flash region 5 is protected
- UNPROTECTED, (1): Data Flash region 5 is not protected
Offset: 6b, Width: 1b, Data Flash Region Protect Bit 6 - Controls protection for 1/8th of the data flash (seventh region)
- PROTECTED, (0): Data Flash region 6 is protected
- UNPROTECTED, (1): Data Flash region 6 is not protected
Offset: 7b, Width: 1b, Data Flash Region Protect Bit 7 - Controls protection for 1/8th of the data flash (eighth region)
- PROTECTED, (0): Data Flash region 7 is protected
- UNPROTECTED, (1): Data Flash region 7 is not protected
Path to FCF configuration or binary file