i.MX 95 Encrypted Boot

This Jupyter notebook demonstrates how to create and deploy encrypted, signed AHAB (Advanced High-Assurance Boot) containers for i.MX95 devices with U-Boot bootloader. This example showcases the complete secure boot chain with both authentication and confidentiality protection.

Key Features

• Individual Image Encryption: Each image within the container is encrypted separately using the same Data Encryption Key (DEK)

• AES-CBC Encryption: Supports AES key sizes of 128, 192, and 256 bits using CBC mode

• Unique IV Generation: Each image uses a unique Initialization Vector (IV) derived from the SHA256 hash of the plaintext image (lower 128 bits used as IV, full 256 bits for integrity verification)

• In-Place Decryption: Images are decrypted directly in memory during boot process

1. Prerequisites

• SPSDK is needed with examples extension. pip install spsdk[examples] (Please refer to the installation documentation.)

• This demo was tested with i.MX 95 EVK board with LPDDR5 memory and B0 chip revision.

1.1 Images preparation

• To create resulting binary containing AHAB containers, we need to prepare the binaries

• Obtain all the necessary binaries and put them into inputs directory

1.2 U-Boot

In order to use the nxpele app, U-Boot must be built with AHAB support. CONFIG_AHAB_BOOT=y If you want to use the nxpele over fastboot, also multiplexing of console output to fastboot must be enabled by setting CONFIG_CONSOLE_MUX=y.

1.3 Requirements

Primary image container set:

• ELE firmware

• LPDDR4 or LPDDR5 firmware files with OEI firmware

• CM33 OEI TCM

• CM33 System manager image

• U-Boot SPL

• [Optional] M7 application image

• Four ECC keys (in this example we use ECC521) - might be created with nxpcrypto tool

• Four ML-DSA keys (in this example we use ML-DSA65) - might be created with nxpcrypto tool

• DEK key for image encryption (in this example we use 128 bits key size)

Secondary image container set:

• ARM Trusted Firmware (bl31.bin binary)

• U-Boot (built with AHAB support)

• TEE binary

• Four ECC keys (Same as in the primary container)

• Four ML-DSA keys (Same as in the primary container)

• DEK key for image encryption (Same as in the primary container)

2. Encryption blob

To encrypt the bootloader we need to prepare DEK key with the desired length and use nxpele generate-keyblob DEK command to generate decryption blob (DEK keyblob), which is device unique. To use this command U-Boot needs to be running on the target device.

Note: See nxpele generate-keyblob DEK --help for more details about command parameters.

DEK_KEY = "../../_data/keys/dek_key.txt"
DEK_KEYBLOB = "outputs/dek_keyblob.bin"

%! nxpele --family mimx9596 generate-keyblob DEK --algorithm AES_CBC --key-id 2 --key $DEK_KEY --key-size 128 --output $DEK_KEYBLOB

nxpele --family mimx9596 generate-keyblob DEK --algorithm AES_CBC --key-id 2 --key ../../_data/keys/dek_key.txt --key-size 128 --output outputs/dek_keyblob.bin 
ELE generate DEK key blob ends successfully:
00480081011003005b8fd715771556d45b18ccd024a6bb2d0940d2252a40b41f48d02700c437a4ac0e1ced00974a1a8dd4167a1a4a3b3b5f2196424dbba09d62707de0c55c32ae83

3. AHAB Image

3.1 AHAB Template

We can generate the template using the nxpimage ahab get-template command. The template is a YAML file that contains the AHAB header and the AHAB container. The AHAB header contains the information about the image, such as the version, the number of containers, and the signature.

The following command generates the template:

nxpimage ahab get-template -f mimx9596 -o ahab_template.yaml

3.2 Exporting of the AHAB image

The AHAB image can be exported using the nxpimage ahab export command. The command will create the AHAB image from the template. The following command creates the AHAB image:

nxpimage ahab export -c ahab_template.yaml 

3.4 Primary image container set

Primary image container set consists of the images mentioned before:

nxpimage ahab get-template -f mimx9596 -o workspace/ahab_template.yaml --force 
Creating workspace/ahab_template.yaml template file.

Configuration Differences

Show Diff Download Config

# ===========================  ahab Configuration template for mimx9596, Revision: latest.  ============================

# ======================================================================================================================
#                                                 == General Options ==                                                 
# ======================================================================================================================
# -------------------------------------===== The chip family name [Required] =====--------------------------------------
# Description: NXP chip family identifier.
family: mimx9596
# -----------------------------------------===== MCU revision [Optional] =====------------------------------------------
# Description: Revision of silicon. The 'latest' name, means most current revision.
# Possible options: 
revision: latest IMPORTANT! Revision B0 has different container format than A1
# -----------------------------------------===== Target memory [Optional] =====-----------------------------------------
# Description: Target memory for AHAB container
# Possible options: 
target_memory: standard
# ---------------------------------------===== Output file name [Required] =====----------------------------------------
# Description: Output AHAB file name
output: generated_ahab.bin
output: ../outputs/primary_encrypted_ahab.bin
# ---------------------------------------===== Container version [Optional] =====---------------------------------------
# Description: Force container version, if not specified the default version is used. This configuration option is valid
# only for chips that supports both AHAB container versions. Possible options <2, 1>
container_version: 2
# ------------------------------===== List of containers present in AHAB [Required] =====-------------------------------
# Description: The order of containers in the list defines the order in AHAB.
containers:
  -
  # ====================================================================================================================
  #                                          == List of possible 2 options. ==                                          
  #                                        Options [binary_container, container]                                        
  # ====================================================================================================================

  #  =========================== [Example of possible configuration: #0 , erase if not used] ============================
    # -----------------------------------===== Binary AHAB container [Required] =====-----------------------------------
    # Description: Binary Container format to add to AHAB image, Typically it could be used to add ELE Firmware.
    binary_container: Define the path to the EdgeLock Enclave Firmware container
      # -----------------------------===== The AHAB container binary file [Required] =====------------------------------
      # Description: The binary file that contains AHAB "my_binary_container.bin
      path: my_ahab_container.bin
      path: ./mx95b0-ahab-container.img

  #  =========================== [Example of possible configuration: #1 , erase if not used] ============================
    # --------------------------------------===== AHAB Container [Required] =====---------------------------------------
  - # --------------------------------------===== AHAB Container [Required] =====---------------------------------------
    # Description: Configurable Container format to add to AHAB image. This allow to configure all aspects of the AHAB
    # container.
    container:
      # --------------------------------===== Super Root Key (SRK) set [Required] =====---------------------------------
      # Description: Defines which set is used to authenticate the container.
      # Possible options: 
      srk_set: none Define set is used to authenticate the container
      srk_set: oem
      # ---------------------------------===== Used SRK [Conditionally required] =====----------------------------------
      # Description: Which key from SRK set is being used.
      used_srk_id: 0
      # -------------------------------------===== SRK revoke mask [Optional] =====-------------------------------------
      # Description: Bit-mask to indicate which SRKs to revoke. Bit set to 1 means revoke key. Bit 0 = revoke SRK_0, bit
      # 1 = revoke SRK_1 etc. Example of revocation SRK_0 and SRK_1 - the value should be 0x03
      srk_revoke_mask: '0x00'
      # ----------------------------------===== GDET runtime behavior [Optional] =====----------------------------------
      # Description: This option defines runtime behavior of Glitch detector. Not supported by all devices and their ELE
      # firmware.
      #  - disabled:       GDET is disabled after the first OEM container has been authenticated (default behavior)
      #  - enabled_eleapi: Automatically enable GDET during all ELE API calls
      #  - enabled:        Leave GDET enabled
      # Possible options: 
      gdet_runtime_behavior: disabled
      # ----------------------------------===== Check all signatures [Optional] =====-----------------------------------
      # Description: This option overrides a fuse to select verification mode.
      #  - default: Apply default fuse policy.
      #  - check_all_signatures: Force verification of all present signatures.
      # Possible options: 
      check_all_signatures: default
      check_all_signatures: check_all_signatures
      # ----------------------------------------===== Fast boot [Optional] =====----------------------------------------
      # Description: This option enables fast boot mode.
      #  - disabled: Fast boot disabled.
      #  - hash_and_copy: ELE will do the hash and copy (when disabled, BootROM will do the copy).
      #  - external_accelerator: Use external accelerator for authentication (e.g. V2X on i.MX95B0, i.MX943 and
      # i.MX952).
      #  - hash_and_copy_with_external_accelerator:ELE will do hash and copy, and use external accelerator for
      # authentication.
      # Possible options: 
      fast_boot: disabled
      # --------------------------------------===== Fuse version [Optional] =====---------------------------------------
      # Description: The value must be equal or greater than the version stored in fuses to allow loading this
      # container.
      fuse_version: 0
      # ------------------------------------===== Software version [Optional] =====-------------------------------------
      # Description: Number used by Privileged Host Boot Companion (PHBC) to select between multiple images with same
      # Fuse version field.
      sw_version: 0
      # ----------------------------------===== AHAB container signer [Optional] =====----------------------------------
      # Description: Signature provider configuration in format 'type=;=;=' or a
      # private key used for sign the container header. Header can be signed by SRK. The referenced SRK must not have
      # been revoked.
      signer: type=file;file_path=my_prv_key.pem Define the path to the private key.
      signer: ../../../_data/keys/ecc384/srk0_ecc521.pem
      # ------------------===== AHAB container signer for second signature (PQC only) [Optional] =====------------------
      # Description: Signature provider configuration in format 'type=;=;=' or a
      # private key used for second sign (PQC only) of the container header. Header can be signed by SRK. The referenced
      # SRK must not have been revoked.
      signer_#2: ../../../_data/keys/mldsa65/srk0_mldsa65.pem
      signer_#2: type=file;file_path=my_prv_key.pem

      # ================================================================================================================
      #                     == Configuration of AHAB Container images (array of multiple images) ==                     
      # ================================================================================================================
      # ---------------------------------------===== Image array [Required] =====---------------------------------------
      # Description: Array of image entries.
      images:
        -
        # ==============================================================================================================
        #                                       == List of possible 13 options. ==                                      
        #      Options [Double Authentication of NXP Firmwares, OEI with DDR tunning images, OEI TCM Settings (ECC      
        # configuration etc.), Boot system manager, Cortex M7 additional application, SPL, V2X Dummy, Uboot ATF, Uboot, 
        #         TEE Trusted Execution Environment, Linux Kernel Image, Device Tree Blob, General Image Entry]         
        # ==============================================================================================================

        #  ===== [Example of possible configuration: #0 Double Authentication of NXP Firmwares, erase if not used] ======
        # Double Authentication of NXP firmwares
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x0000000000000000
        # hash_type:                     SHA384
          # -------------------------------------===== NXP ELE FW [Required] =====--------------------------------------
          # Description: NXP ELE firmware, that should be also signed by OEM keys binary file.
          double_authentication: nxp_ele.bin

        #  =========== [Example of possible configuration: #1 OEI with DDR tunning images, erase if not used] ===========
        # OEI with DDR PHY tunning images
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000001FFC0000
        # entry_point:                   0x000000001FFC0001
        # image_type:                    oei
        # core_id:                       cortex-m33
        # hash_type:                     SHA384
          # -----------------------------------===== LPDDR memory FW [Required] =====-----------------------------------
          # Description: Firmware for LPDDR4/5 memory.
          lpddr_imem: lpddr_imem.bin Add path to the LPDDR IMEM image
          lpddr_imem: ./lpddr5_imem_v202409.bin
          # ---------------------------===== LPDDR memory FW for quick boot [Optional] =====----------------------------
          # Description: Firmware for LPDDR4/5 for quick boot.
          lpddr_imem_qb: lpddr_imem_qb.bin Add path to the LPDDR IMEM image
          lpddr_imem_qb: ./lpddr5_imem_qb_v202409.bin
          # ----------------------------------===== LPDDR memory data [Required] =====----------------------------------
          # Description: Data for LPDDR4/5 memory.
          lpddr_dmem: lpddr_dmem.bin Add path to the LPDDR DMEM image
          lpddr_dmem: ./lpddr5_dmem_v202409.bin
          # --------------------------===== LPDDR memory data for quick boot [Optional] =====---------------------------
          # Description: Data for LPDDR4/5 memory in quick boot.
          lpddr_dmem_qb: lpddr_dmem_qb.bin Optionally add path to the LPDDR DMEM quick boot image
          lpddr_dmem_qb: ./lpddr5_dmem_qb_v202409.bin
          # -----------------------------------------===== OEI [Required] =====-----------------------------------------
          # Description: OEI - Optional Executable Image firmware
          oei_ddr: oei_ddr.bin Add path to the OEI DDR image
          oei_ddr: ./oei-m33-ddr.bin
          is_encrypted: true
          # -----------------------------------===== Quick Boot Data [Optional] =====-----------------------------------
          # Description: QB data - Optional Quick boot data, if defined a new empty record will be added just behind DDR
          # FW entry
          qb_data: qb_data.bin

        #  ==== [Example of possible configuration: #2 OEI TCM Settings (ECC configuration etc.), erase if not used] ====
        # OEI TCM settings (ECC etc.)
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000001FFC0000
        # entry_point:                   0x000000001FFC0001
        # image_type:                    oei
        # core_id:                       cortex-m33
        # hash_type:                     SHA384
          # -------------------------------------===== OEI TCM FW [Required] =====--------------------------------------
          # Description: OEI(Optional Executable Image) TCM settings binary file.
          oei_tcm: oei_tcm.bin Add path to the OEI TCM image
        - oei_tcm: ./oei-m33-tcm.bin
          is_encrypted: true

        #  =============== [Example of possible configuration: #3 Boot system manager, erase if not used] ===============
        # System booting image
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000001FFC0000
        # image_type:                    executable
        # core_id:                       cortex-m33
        # hash_type:                     SHA384
          # ---------------------------------===== Boot system manager [Required] =====---------------------------------
          # Description: System manager booting image
          system_manager: system_manager.bin Add path to system manager
        - system_manager: ./m33_image-mx95evk.bin
          is_encrypted: true

        #  ======== [Example of possible configuration: #4 Cortex M7 additional application, erase if not used] =========
        # Cortex M7 additional application
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x00000000303C0000
        # entry_point:                   0x0000000000000000
        # image_type:                    executable
        # core_id:                       cortex-m7-1
        # meta_data_start_cpu_id:        1
        # hash_type:                     SHA384
          # --------------------------===== Cortex M7 additional application [Required] =====---------------------------
          # Description: Cortex M7 additional application
        - cortex_m7_app: ./hello_world_sm_cm7.bin
          is_encrypted: true
          cortex_m7_app: cortex_m7_app.bin Optionally Add path to the Cortex M7 application

        #  ======================= [Example of possible configuration: #5 SPL, erase if not used] =======================
        # U-Boot SPL (Secondary program loader)
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x0000000020480000
        # image_type:                    executable
        # core_id:                       cortex-a55
        # meta_data_start_cpu_id:        2
        # hash_type:                     SHA384
          # -----------------------------------------===== SPL [Required] =====-----------------------------------------
          # Description: SPL firmware
        - spl: ./u-boot-spl_mx95_19x19.bin
          is_encrypted: true
          spl: spl.bin Add path to the U-Boot SPL image

        #  ==================== [Example of possible configuration: #6 V2X Dummy, erase if not used] ====================
        # V2X dummy image container definition
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000008B000000
        # image_type:                    v2x_dummy
        # core_id:                       cortex-m33
        # hash_type:                     SHA384
          # --------------------------------------===== V2X Dummy [Required] =====--------------------------------------
          # Description: If Present, V2X dummy image will be added to Image Array Entry (no data record)
          v2x_dummy: true This is a dummy image that has to be present in the container for A0
        - v2x_dummy: true

        #  ==================== [Example of possible configuration: #7 Uboot ATF, erase if not used] ====================
        # U-Boot ATF container definition
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000008A200000
        # image_type:                    executable
        # core_id:                       cortex-a55
        # meta_data_start_cpu_id:        2
        # hash_type:                     SHA384
          # -------------------------------------===== ATF binary [Required] =====--------------------------------------
          # Description: ARM Trusted Firmware binary file.
          atf: bl31.bin

        #  ====================== [Example of possible configuration: #8 Uboot, erase if not used] ======================
        # U-Boot container definition
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x0000000090200000
        # image_type:                    executable
        # core_id:                       cortex-a55
        # meta_data_start_cpu_id:        2
        # hash_type:                     SHA384
          # ------------------------------------===== U-Boot binary [Required] =====------------------------------------
          # Description: U-Boot binary file.
          uboot: u-boot.bin

        #  ======== [Example of possible configuration: #9 TEE Trusted Execution Environment, erase if not used] ========
        # A TEE (Trusted Execution Environment) is a trusted OS running in some secure environment, for example, TrustZone on ARM CPUs, or a separate secure co-processor etc. A TEE driver handles the details needed to communicate with the TEE.
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000008C000000
        # image_type:                    executable
        # core_id:                       cortex-a55
        # meta_data_start_cpu_id:        2
        # hash_type:                     SHA384
          # -----------------------------------------===== TEE [Required] =====-----------------------------------------
          # Description: TEE - Trusted Execution Environment binary
          tee: tee.bin

        #  =============== [Example of possible configuration: #10 Linux Kernel Image, erase if not used] ===============
        # Linux kernel Image container definition
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x0000000090400000
        # image_type:                    executable
        # core_id:                       cortex-a55
        # meta_data_start_cpu_id:        2
        # hash_type:                     SHA384
          # ------------------------------===== Linux Kernel Image Binary [Required] =====------------------------------
          # Description: Linux kernel executable Image binary file (typically Image.bin)
          kernel: Image.bin

        #  ================ [Example of possible configuration: #11 Device Tree Blob, erase if not used] ================
        # Device Tree Blob (DTB) container definition
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x0000000093000000
        # entry_point:                   0x0000000000000000
        # image_type:                    data
        # core_id:                       cortex-a55
        # hash_type:                     SHA384
          # -------------------------------===== Device Tree Blob Binary [Required] =====-------------------------------
          # Description: Device Tree Blob (DTB) binary file containing hardware description
          dtb: device-tree.dtb

        #  ============== [Example of possible configuration: #12 General Image Entry, erase if not used] ===============
        # General Image Entry
          # -------------------------------------===== Image path [Optional] =====--------------------------------------
          # Description: Path to image binary (absolute/relative). In case that only Image Array entry without any data
          # image is needed, Just do not use the image path. In case that the image size in container should be aligned
          # differently then SPSDK do (4 bytes for ELE images, 1 byte otherwise), there is hidden option
          # 'image_size_alignment' where could be override image size by any custom value.
          image_path: my_image.bin
          # ---------------------------===== Image offset in AHAB container [Optional] =====----------------------------
          # Description: Offset in bytes from start of container header to beginning of the image. Zero value means
          # automatic placing the image with proper alignment after previous one, this is recommended for
          # serial_downloader mode. In case of XiP type of AHAB image, the load_address and entry_point must correspond
          # to this values. Example of setting of load_address - AHAB_IMAGE_ADDRESS+IMAGE_OFFSET=LOAD_ADDRESS. The
          # Booting core images must be located after the other ones
          image_offset: 0
          # ------------------------------===== Image destination address [Required] =====------------------------------
          # Description: Address the image is written to in memory (absolute address in system memory).
          load_address: '0x1FFC_0000'
          # ----------------------------------===== Image entry point [Required] =====----------------------------------
          # Description: Image entry point (absolute address). Valid only for executable image types.
          entry_point: '0x1FFC_0000'
          # -------------------------------------===== Image type [Required] =====--------------------------------------
          # Description: Kind of image.
          # Possible options: 
          # executable_fast_boot_image, oei_ddr, v2x_dummy, ele_as_image, ele, v2x_as_image, v2x_primary, v2x_secondary,
          # v2x_rom_patch>
          image_type: executable
          # ---------------------------------------===== Core ID [Required] =====---------------------------------------
          # Description: Defines the core the image is dedicated for. Not all cores are supported for all families.
          # Possible options: 
          core_id: dummy
          # ----------------------------------===== Image encryption [Optional] =====-----------------------------------
          # Description: Determines, whether image is encrypted or not.
          is_encrypted: false Set true for each image you want to encrypt
          is_encrypted: true
          # -------------------------------------===== Boot flags [Optional] =====--------------------------------------
          # Description: Boot flags controlling SCFW boot.
          boot_flags: 0
          # ------------------------------------===== Start CPU ID [Optional] =====-------------------------------------
          # Description: Resource ID of CPU to be started
          meta_data_start_cpu_id: 0
          # ------------------------------===== CPU memory unit start ID [Optional] =====-------------------------------
          # Description: Resource ID of the MU associated with the CPU
          meta_data_mu_cpu_id: 0
          # ---------------------------------===== Start partition ID [Optional] =====----------------------------------
          # Description: Partition ID of the partition to start
          meta_data_start_partition_id: 0
          # ----------------------------------===== Images HASH type [Optional] =====-----------------------------------
          # Description: HASH type of image.
          # Possible options: 
          hash_type: sha512

      # ================================================================================================================
      #                                      == Configuration of AHAB SRK table ==                                      
      # ================================================================================================================
      # ---------------------------------===== SRK Table [Conditionally required] =====---------------------------------
      # Description: SRK (Super Root key) table definition.
      srk_table: All attributes related to the signing
        # ----------------------------------------===== CA Flag [Optional] =====----------------------------------------
        # Description: CA Flag is used by HAB to indicate if the SRK is allowed to sign other keys. In AHAB CA Flag only
        # affects the final SRKH (Super Root Key Hash) value burned into chip fuses. It is not used in the AHAB signing
        # process itself. This option exists only for compatibility with systems where fuses are already programmed. In
        # most cases, this should remain false.
        flag_ca: false
        # ------------------------------------===== Hash Algorithm [Optional] =====-------------------------------------
        # Description: Hash algorithm used for SRK records. If not specified, default algorithm based on key type will
        # be used.
        # Possible options: 
        # shake_256_512, sm3>
        hash_algorithm: default
        hash_algorithm: sha3_512
        # ------------------------------===== Super Root Key (SRK) table [Required] =====-------------------------------
        # Description: Table containing the used SRK records. All SRKs must be of the same type. Supported signing
        # algorithms are: RSA-PSS, ECDSA, Dilithium or SM2. Supported hash algorithms: sha256, sha384, sha512, sha3_256,
        # sha3_384, sha3_512, sm3. Supported key sizes/curves: prime256v1, sec384r1, sec512r1, rsa2048, rsa4096,
        # dilithium3, sm2. Certificate may be of Certificate Authority. Dilithium algorithms are supported just in new
        # type of AHAB container
        srk_array:
          - my_srk_public_key0.pub
          - my_srk_public_key1.pub
          - my_srk_public_key2.pub
          - my_srk_public_key3.pub
          - ../../../_data/keys/ecc521/srk0_ecc521.pub
          - ../../../_data/keys/ecc521/srk1_ecc521.pub
          - ../../../_data/keys/ecc521/srk2_ecc521.pub
          - ../../../_data/keys/ecc521/srk3_ecc521.pub

        # ==============================================================================================================
        #               == Configuration of AHAB SRK table in case that the double signing (ECC + PQC) ==               
        # ==============================================================================================================
        # -----------------------------------===== Second SRK Table [Optional] =====------------------------------------
        srk_table_#2:
          # ---------------------------------------===== CA Flag [Optional] =====---------------------------------------
          # Description: CA Flag is used by AHAB to indicate if the SRK is allowed to sign other keys. In AHAB CA Flag
          # only affects the final SRKH (Super Root Key Hash) value burned into chip fuses. It is not used in the AHAB
          # signing process itself. This option exists only for compatibility with systems where fuses are already
          # programmed. In most cases, this should remain false.
          flag_ca: false
          # -----------------------------------===== Hash Algorithm [Optional] =====------------------------------------
          # Description: Hash algorithm used for SRK records. If not specified, default algorithm based on key type will
          # be used.
          # Possible options: 
          # shake_256_512, sm3>
          hash_algorithm: default
          hash_algorithm: sha3_512
          # -----------------------------===== Super Root Key (SRK) table [Required] =====------------------------------
          # Description: Table containing the used SRK Dilithium records. All SRKs must be of the same type. Supported
          # signing algorithms are: Dilithium level 3. Supported hash algorithms: sha3_256, sha3_384, sha3_512.
          # Certificate may be of Certificate Authority.
          srk_array:
            - my_srk_public_key0.pub
            - my_srk_public_key1.pub
            - my_srk_public_key2.pub
            - my_srk_public_key3.pub
            - ../../../_data/keys/mldsa65/srk0_mldsa65.pub
            - ../../../_data/keys/mldsa65/srk1_mldsa65.pub
            - ../../../_data/keys/mldsa65/srk2_mldsa65.pub
            - ../../../_data/keys/mldsa65/srk3_mldsa65.pub

      # ================================================================================================================
      #           == Optional configuration of AHAB Container Certificate (if not used, erase the section) ==           
      # ================================================================================================================
      # ----------------------------------===== The AHAB certificate [Optional] =====-----------------------------------
      # Description: The file that contains AHAB certificate. It could be used already prepared binary form signed by
      # SRK, or it is possible to use configuration YAML file of certificate and the AHAB export process it will export
      # it itself.
      certificate: my_ahab_certificate.bin

      # ================================================================================================================
      #         == Optional configuration of AHAB Container Encryption blob (if not used, erase the section) ==         
      # ================================================================================================================
      # -------------------------------------===== Encryption blob [Optional] =====-------------------------------------
      # Description: Encryption blob container definition
      blob:
        blob:
        # ------------------------------------===== Key identifier [Required] =====-------------------------------------
        # Description: The key identifier that has been used to generate DEK keyblob.
        key_identifier: 0 All attributes related to the encrypting
          key_identifier: 2
        # -------------------------------------===== DEK key size [Required] =====--------------------------------------
        # Description: Data Encryption key size. Used for AES CBC-MAC (128/192/256 size)
        # Possible options: <128, 192, 256>
        dek_key_size: 128
          dek_key_size: 128
        # ----------------------------------------===== DEK key [Required] =====----------------------------------------
        # Description: Data Encryption key. Used for AES CBC-MAC (128/192/256 size). The HEX format is accepted
        dek_key: my_dek_key.txt
          dek_key: ../../../_data/keys/dek_key.txt
        # --------------------------------------===== DEK keyblob [Optional] =====--------------------------------------
        # Description: Wrapped Data Encryption key. Used for AES CBC-MAC (128/192/256 size). The HEX format is accepted.
        # If NOT used, the empty keyblob is inserted into container and need to be updated later.
        dek_keyblob: my_wrapped_key.txt
          dek_keyblob: ./outputs/dek_keyblob.bin

# Copyright 2025 NXP
#
# SPDX-License-Identifier: BSD-3-Clause
# ==========================  Advanced High-Assurance Boot Configuration template for mimx9596.  ===========================

# ======================================================================================================================
#                                                 == General Options ==
# ======================================================================================================================
# ------------------------------------------===== MCU family [Required] =====-------------------------------------------
# Description: Family identifier including the chip revision. If revision is not present, latest revision is used as
# default.
# Possible options: 
family: mimx9596
# -----------------------------------------===== MCU revision [Optional] =====------------------------------------------
# Description: Revision of silicon
revision: latest IMPORTANT! Revision B0 has different container format than A1
# ----------------------------------===== Target memory [Conditionally required] =====----------------------------------
# Description: Target memory for AHAB container
# Possible options: 
target_memory: standard
# ---------------------------------------===== Output file name [Required] =====----------------------------------------
# Description: Output AHAB file name
output: ../outputs/primary_encrypted_ahab.bin
# ---------------------------------------===== Container version [Optional] =====---------------------------------------
# Description: Force container version, if not specified the default version is used. This configuration option is valid
# only for chips that supports both AHAB container versions. Possible options <2, 1>
container_version: 2
# ------------------------------===== List of containers present in AHAB [Required] =====-------------------------------
# Description: The order of containers in the list defines the order in AHAB.
containers:
  -
    # -----------------------------------===== Binary AHAB container [Required] =====-----------------------------------
    # Description: Binary Container format to add to AHAB image, Typically it could be used to add ELE Firmware.
    binary_container: Define the path to the EdgeLock Enclave Firmware container
      # -----------------------------===== The AHAB container binary file [Required] =====------------------------------
      # Description: The binary file that contains AHAB "my_binary_container.bin
      path: ./mx95b0-ahab-container.img

  - # --------------------------------------===== AHAB Container [Required] =====---------------------------------------
    # Description: Configurable Container format to add to AHAB image. This allow to configure all aspects of the AHAB
    # container.
    container:
      # --------------------------------===== Super Root Key (SRK) set [Required] =====---------------------------------
      # Description: Defines which set is used to authenticate the container.
      # Possible options: 
      srk_set: oem Define set is used to authenticate the container
      # ---------------------------------===== Used SRK [Conditionally required] =====----------------------------------
      # Description: Which key from SRK set is being used.
      used_srk_id: 0
      # -------------------------------------===== SRK revoke mask [Optional] =====-------------------------------------
      # Description: Bit-mask to indicate which SRKs to revoke. Bit set to 1 means revoke key. Bit 0 = revoke SRK_0, bit
      # 1 = revoke SRK_1 etc. Example of revocation SRK_0 and SRK_1 - the value should be 0x03
      srk_revoke_mask: '0x00'
      # ----------------------------------===== GDET runtime behavior [Optional] =====----------------------------------
      # Description: This option defines runtime behavior of Glitch detector. Not supported by all devices and their ELE
      # firmware.
      #  - disabled:       GDET is disabled after the first OEM container has been authenticated (default behavior)
      #  - enabled_eleapi: Automatically enable GDET during all ELE API calls
      #  - enabled:        Leave GDET enabled
      # Possible options: 
      gdet_runtime_behavior: disabled
      # ----------------------------------===== Check all signatures [Optional] =====-----------------------------------
      # Description: This option overrides a fuse to select verification mode.
      #  - default: Apply default fuse policy.
      #  - check_all_signatures: Force verification of all present signatures.
      # Possible options: 
      check_all_signatures: check_all_signatures
      # ----------------------------------------===== Fast boot [Optional] =====----------------------------------------
      # Description: This option enables fast boot mode.
      #  - disabled: Fast boot disabled.
      #  - hash_and_copy: ELE will do the hash and copy (when disabled, BootROM will do the copy).
      #  - external_accelerator: Use external accelerator for authentication (e.g. V2X on i.MX95B0, i.MX943 and
      # i.MX952).
      #  - hash_and_copy_with_external_accelerator:ELE will do hash and copy, and use external accelerator for
      # authentication.
      # Possible options: 
      fast_boot: disabled
      # --------------------------------------===== Fuse version [Optional] =====---------------------------------------
      # Description: The value must be equal or greater than the version stored in fuses to allow loading this
      # container.
      fuse_version: 0
      # ------------------------------------===== Software version [Optional] =====-------------------------------------
      # Description: Number used by Privileged Host Boot Companion (PHBC) to select between multiple images with same
      # Fuse version field.
      sw_version: 0
      # -------------------------------===== AHAB container signing key [Optional] =====--------------------------------
      # Description: Private key used for sign the container header. Header can be signed by SRK. The referenced SRK
      # must not have been revoked.
      signer: ../../../_data/keys/ecc384/srk0_ecc521.pem Define the path to the private key.
      # ------------------===== AHAB container signer for second signature (PQC only) [Optional] =====------------------
      # Description: Signature provider configuration in format 'type=;=;=' or a
      # private key used for second sign (PQC only) of the container header. Header can be signed by SRK. The referenced
      # SRK must not have been revoked.
      signer_#2: ../../../_data/keys/mldsa65/srk0_mldsa65.pem
      # ================================================================================================================
      #                     == Configuration of AHAB Container images (array of multiple images) ==
      # ================================================================================================================
      # ---------------------------------------===== Image array [Required] =====---------------------------------------
      # Description: Array of image entries.
      images:
        -
          # OEI with DDR PHY tunning images
          # Image array default settings. Can be override by defines that are hidden in template:
          # image_offset:                  0x00010400
          # load_address:                  0x000000001FFC0000
          # entry_point:                   0x000000001FFC0001
          # image_type:                    executable
          # core_id:                       cortex-m33
          # hash_type:                     SHA384
          # -----------------------------===== LPDDR memory FW in 1D mode [Required] =====------------------------------
          # Description: Firmware for LPDDR4/5 memory in 1D mode.
          lpddr_imem: ./lpddr5_imem_v202409.bin Add path to the LPDDR IMEM image
          # -----------------------------===== LPDDR memory FW in 2D mode [Required] =====------------------------------
          # Description: Firmware for LPDDR4/5 memory in 2D mode.
          lpddr_imem_qb: ./lpddr5_imem_qb_v202409.bin Add path to the LPDDR IMEM image
          # ----------------------------===== LPDDR memory data in 1D mode [Required] =====-----------------------------
          # Description: Data for LPDDR4/5 memory in 1D mode.
          lpddr_dmem: ./lpddr5_dmem_v202409.bin Add path to the LPDDR DMEM image
          # ----------------------------===== LPDDR memory data in 2D mode [Required] =====-----------------------------
          # Description: Data for LPDDR4/5 memory in 2D mode.
          lpddr_dmem_qb: ./lpddr5_dmem_qb_v202409.bin Optionally add path to the LPDDR DMEM quick boot image
          # -----------------------------------------===== OEI [Required] =====-----------------------------------------
          # Description: OEI - Optional Executable Image firmware
          oei_ddr: ./oei-m33-ddr.bin Add path to the OEI DDR image
          is_encrypted: true Set true for each image you want to encrypt
          # OEI TCM settings (ECC etc.)
          # Image array default settings. Can be override by defines that are hidden in template:
          # image_offset:                  0x00010400
          # load_address:                  0x000000001FFC0000
          # entry_point:                   0x000000001FFC0001
          # image_type:                    executable
          # core_id:                       cortex-m33
          # hash_type:                     SHA384
          # -------------------------------------===== OEI TCM FW [Required] =====--------------------------------------
          # Description: OEI(Optional Executable Image) TCM settings binary file.
        - oei_tcm: ./oei-m33-tcm.bin Add path to the OEI TCM image
          is_encrypted: true Set true for each image you want to encrypt
          # System booting image
          # Image array default settings. Can be override by defines that are hidden in template:
          # image_offset:                  0x00080400
          # load_address:                  0x000000001FFC0000
          # image_type:                    executable
          # core_id:                       cortex-m33
          # hash_type:                     SHA384
          # ---------------------------------===== Boot system manager [Required] =====---------------------------------
          # Description: System manager booting image
        - system_manager: ./m33_image-mx95evk.bin Add path to system manager
          is_encrypted: true Set true for each image you want to encrypt
          # Cortex M7 additional application
          # Image array default settings. Can be override by defines that are hidden in template:
          # load_address:                  0x00000000303C0000
          # image_type:                    executable
          # core_id:                       cortex-m7-1
          # hash_type:                     SHA384
          # --------------------------===== Cortex M7 additional application [Required] =====---------------------------
          # Description: Cortex M7 additional application
        - cortex_m7_app: ./hello_world_sm_cm7.bin Optionally Add path to the Cortex M7 application
          is_encrypted: true Set true for each image you want to encrypt
          # U-Boot SPL (Secondary program loader)
          # Image array default settings. Can be override by defines that are hidden in template:
          # image_offset:                  0x00010400
          # load_address:                  0x0000000020480000
          # image_type:                    executable
          # core_id:                       cortex-a55
          # hash_type:                     SHA384
          # -----------------------------------------===== SPL [Required] =====-----------------------------------------
          # Description: SPL firmware
        - spl: ./u-boot-spl_mx95_19x19.bin Add path to the U-Boot SPL image
          is_encrypted: true Set true for each image you want to encrypt
          # V2X dummy image container definition
          # Image array default settings. Can be override by defines that are hidden in template:
          # load_address:                  0x000000008B000000
          # image_type:                    v2x_dummy
          # core_id:                       cortex-m33
          # hash_type:                     SHA384
          # --------------------------------------===== V2X Dummy [Required] =====--------------------------------------
          # Description: If Present, V2X dummy image will be added to Image Array Entry (no data record)
        - v2x_dummy: true This is a dummy image that has to be present in the container for A0
          is_encrypted: true Set true for each image you want to encrypt
      # ================================================================================================================
      #                                      == Configuration of AHAB SRK table ==
      # ================================================================================================================
      # ---------------------------------===== SRK Table [Conditionally required] =====---------------------------------
      # Description: SRK (Super Root key) table definition.
      srk_table: All attributes related to the signing
        # ----------------------------------------===== CA Flag [Optional] =====----------------------------------------
        # Description: CA Flag is used by HAB to indicate if the SRK is allowed to sign other keys
        flag_ca: false
        # ------------------------------------===== Hash Algorithm [Optional] =====-------------------------------------
        # Description: Hash algorithm used for SRK records. If not specified, default algorithm based on key type will
        # be used.
        # Possible options: 
        hash_algorithm: sha3_512
        # ------------------------------===== Super Root Key (SRK) table [Required] =====-------------------------------
        # Description: Table containing the used SRK records. All SRKs must be of the same type. Supported signing
        # algorithms are: RSA-PSS, ECDSA, Dilithium or SM2. Supported hash algorithms: sha256, sha384, sha512, sha3_256,
        # sha3_384, sha3_512, sm3. Supported key sizes/curves: prime256v1, sec384r1, sec512r1, rsa2048, rsa4096,
        # dilithium3, sm2. Certificate may be of Certificate Authority. Dilithium algorithms are supported just in new
        # type of AHAB container
        srk_array:
          - ../../../_data/keys/ecc521/srk0_ecc521.pub
          - ../../../_data/keys/ecc521/srk1_ecc521.pub
          - ../../../_data/keys/ecc521/srk2_ecc521.pub
          - ../../../_data/keys/ecc521/srk3_ecc521.pub

        # ==============================================================================================================
        #               == Configuration of AHAB SRK table in case that the double signing (ECC + PQC) ==               
        # ==============================================================================================================
        # -----------------------------------===== Second SRK Table [Optional] =====------------------------------------
        srk_table_#2:
          # ---------------------------------------===== CA Flag [Optional] =====---------------------------------------
          # Description: CA Flag is used by AHAB to indicate if the SRK is allowed to sign other keys. In AHAB CA Flag
          # only affects the final SRKH (Super Root Key Hash) value burned into chip fuses. It is not used in the AHAB
          # signing process itself. This option exists only for compatibility with systems where fuses are already
          # programmed. In most cases, this should remain false.
          flag_ca: false
          # -----------------------------------===== Hash Algorithm [Optional] =====------------------------------------
          # Description: Hash algorithm used for SRK records. If not specified, default algorithm based on key type will
          # be used.
          # Possible options: 
          hash_algorithm: sha3_512
          # -----------------------------===== Super Root Key (SRK) table [Required] =====------------------------------
          # Description: Table containing the used SRK Dilithium records. All SRKs must be of the same type. Supported
          # signing algorithms are: Dilithium level 3. Supported hash algorithms: sha3_256, sha3_384, sha3_512.
          # Certificate may be of Certificate Authority.
          srk_array:
            - ../../../_data/keys/mldsa65/srk0_mldsa65.pub
            - ../../../_data/keys/mldsa65/srk1_mldsa65.pub
            - ../../../_data/keys/mldsa65/srk2_mldsa65.pub
            - ../../../_data/keys/mldsa65/srk3_mldsa65.pub

        # ================================================================================================================
        #         == Optional configuration of AHAB Container Encryption blob (if not used, erase the section) ==         
        # ================================================================================================================
        # -------------------------------------===== Encryption blob [Optional] =====-------------------------------------
        # Description: Encryption blob container definition
        blob:
          # ------------------------------------===== Key identifier [Required] =====-------------------------------------
          # Description: The key identifier that has been used to generate DEK keyblob.
          key_identifier: 2 All attributes related to the encrypting
          # -------------------------------------===== DEK key size [Required] =====--------------------------------------
          # Description: Data Encryption key size. Used for AES CBC-MAC (128/192/256 size)
          # Possible options: <128, 192, 256>
          dek_key_size: 128
          # ----------------------------------------===== DEK key [Required] =====----------------------------------------
          # Description: Data Encryption key. Used for AES CBC-MAC (128/192/256 size). The HEX format is accepted
          dek_key: ../../../_data/keys/dek_key.txt
          # --------------------------------------===== DEK keyblob [Optional] =====--------------------------------------
          # Description: Wrapped Data Encryption key. Used for AES CBC-MAC (128/192/256 size). The HEX format is accepted.
          # If NOT used, the empty keyblob is inserted into container and need to be updated later.
          dek_keyblob: ./outputs/dek_keyblob.bin

3.5 Secondary image container set

Secondary image container set consists of the images mentioned before:

YamlDiffWidget("inputs/mx95_encrypted_ahab_secondary.diffc").html

nxpimage ahab get-template -f mimx9596 -o workspace/ahab_template.yaml --force 
Creating workspace/ahab_template.yaml template file.

Configuration Differences

Show Diff Download Config

# ===========================  ahab Configuration template for mimx9596, Revision: latest.  ============================

# ======================================================================================================================
#                                                 == General Options ==                                                 
# ======================================================================================================================
# -------------------------------------===== The chip family name [Required] =====--------------------------------------
# Description: NXP chip family identifier.
family: mimx9596
# -----------------------------------------===== MCU revision [Optional] =====------------------------------------------
# Description: Revision of silicon. The 'latest' name, means most current revision.
# Possible options: 
revision: latest IMPORTANT! Revision B0 has different container format than A1
# -----------------------------------------===== Target memory [Optional] =====-----------------------------------------
# Description: Target memory for AHAB container
# Possible options: 
target_memory: standard
# ---------------------------------------===== Output file name [Required] =====----------------------------------------
# Description: Output AHAB file name
output: generated_ahab.bin
output: ../outputs/secondary_encrypted_ahab.bin
# ---------------------------------------===== Container version [Optional] =====---------------------------------------
# Description: Force container version, if not specified the default version is used. This configuration option is valid
# only for chips that supports both AHAB container versions. Possible options <2, 1>
container_version: 2
# ------------------------------===== List of containers present in AHAB [Required] =====-------------------------------
# Description: The order of containers in the list defines the order in AHAB.
containers:
  -
  # ====================================================================================================================
  #                                          == List of possible 2 options. ==                                          
  #                                        Options [binary_container, container]                                        
  # ====================================================================================================================

  #  =========================== [Example of possible configuration: #0 , erase if not used] ============================
    # -----------------------------------===== Binary AHAB container [Required] =====-----------------------------------
    # Description: Binary Container format to add to AHAB image, Typically it could be used to add ELE Firmware.
    binary_container:
      # -----------------------------===== The AHAB container binary file [Required] =====------------------------------
      # Description: The binary file that contains AHAB "my_binary_container.bin
      path: my_ahab_container.bin

  #  =========================== [Example of possible configuration: #1 , erase if not used] ============================
    # --------------------------------------===== AHAB Container [Required] =====---------------------------------------
  - # --------------------------------------===== AHAB Container [Required] =====---------------------------------------
    # Description: Configurable Container format to add to AHAB image. This allow to configure all aspects of the AHAB
    # container.
    container:
      # --------------------------------===== Super Root Key (SRK) set [Required] =====---------------------------------
      # Description: Defines which set is used to authenticate the container.
      # Possible options: 
      srk_set: none Define set is used to authenticate the container
      srk_set: oem
      # ---------------------------------===== Used SRK [Conditionally required] =====----------------------------------
      # Description: Which key from SRK set is being used.
      used_srk_id: 0
      # -------------------------------------===== SRK revoke mask [Optional] =====-------------------------------------
      # Description: Bit-mask to indicate which SRKs to revoke. Bit set to 1 means revoke key. Bit 0 = revoke SRK_0, bit
      # 1 = revoke SRK_1 etc. Example of revocation SRK_0 and SRK_1 - the value should be 0x03
      srk_revoke_mask: '0x00'
      srk_revoke_mask: "0x00"
      # ----------------------------------===== GDET runtime behavior [Optional] =====----------------------------------
      # Description: This option defines runtime behavior of Glitch detector. Not supported by all devices and their ELE
      # firmware.
      #  - disabled:       GDET is disabled after the first OEM container has been authenticated (default behavior)
      #  - enabled_eleapi: Automatically enable GDET during all ELE API calls
      #  - enabled:        Leave GDET enabled
      # Possible options: 
      gdet_runtime_behavior: disabled
      # ----------------------------------===== Check all signatures [Optional] =====-----------------------------------
      # Description: This option overrides a fuse to select verification mode.
      #  - default: Apply default fuse policy.
      #  - check_all_signatures: Force verification of all present signatures.
      # Possible options: 
      check_all_signatures: default
      check_all_signatures: check_all_signatures
      # ----------------------------------------===== Fast boot [Optional] =====----------------------------------------
      # Description: This option enables fast boot mode.
      #  - disabled: Fast boot disabled.
      #  - hash_and_copy: ELE will do the hash and copy (when disabled, BootROM will do the copy).
      #  - external_accelerator: Use external accelerator for authentication (e.g. V2X on i.MX95B0, i.MX943 and
      # i.MX952).
      #  - hash_and_copy_with_external_accelerator:ELE will do hash and copy, and use external accelerator for
      # authentication.
      # Possible options: 
      fast_boot: disabled
      # --------------------------------------===== Fuse version [Optional] =====---------------------------------------
      # Description: The value must be equal or greater than the version stored in fuses to allow loading this
      # container.
      fuse_version: 0
      # ------------------------------------===== Software version [Optional] =====-------------------------------------
      # Description: Number used by Privileged Host Boot Companion (PHBC) to select between multiple images with same
      # Fuse version field.
      sw_version: 0
      # ----------------------------------===== AHAB container signer [Optional] =====----------------------------------
      # Description: Signature provider configuration in format 'type=;=;=' or a
      # private key used for sign the container header. Header can be signed by SRK. The referenced SRK must not have
      # been revoked.
      signer: type=file;file_path=my_prv_key.pem
      signer: ../../../_data/keys/ecc521/srk0_ecc521.pem
      # ------------------===== AHAB container signer for second signature (PQC only) [Optional] =====------------------
      # Description: Signature provider configuration in format 'type=;=;=' or a
      # private key used for second sign (PQC only) of the container header. Header can be signed by SRK. The referenced
      # SRK must not have been revoked.
      signer_#2: type=file;file_path=my_prv_key.pem
      signer_#2: ../../../_data/keys/mldsa65/srk0_mldsa65.pem

      # ================================================================================================================
      #                     == Configuration of AHAB Container images (array of multiple images) ==                     
      # ================================================================================================================
      # ---------------------------------------===== Image array [Required] =====---------------------------------------
      # Description: Array of image entries.
      images:
        -
        # ==============================================================================================================
        #                                       == List of possible 13 options. ==                                      
        #      Options [Double Authentication of NXP Firmwares, OEI with DDR tunning images, OEI TCM Settings (ECC      
        # configuration etc.), Boot system manager, Cortex M7 additional application, SPL, V2X Dummy, Uboot ATF, Uboot, 
        #         TEE Trusted Execution Environment, Linux Kernel Image, Device Tree Blob, General Image Entry]         
        # ==============================================================================================================

        #  ===== [Example of possible configuration: #0 Double Authentication of NXP Firmwares, erase if not used] ======
        # Double Authentication of NXP firmwares
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x0000000000000000
        # hash_type:                     SHA384
          # -------------------------------------===== NXP ELE FW [Required] =====--------------------------------------
          # Description: NXP ELE firmware, that should be also signed by OEM keys binary file.
          double_authentication: nxp_ele.bin

        #  =========== [Example of possible configuration: #1 OEI with DDR tunning images, erase if not used] ===========
        # OEI with DDR PHY tunning images
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000001FFC0000
        # entry_point:                   0x000000001FFC0001
        # image_type:                    oei
        # core_id:                       cortex-m33
        # hash_type:                     SHA384
          # -----------------------------------===== LPDDR memory FW [Required] =====-----------------------------------
          # Description: Firmware for LPDDR4/5 memory.
          lpddr_imem: lpddr_imem.bin
          # ---------------------------===== LPDDR memory FW for quick boot [Optional] =====----------------------------
          # Description: Firmware for LPDDR4/5 for quick boot.
          lpddr_imem_qb: lpddr_imem_qb.bin
          # ----------------------------------===== LPDDR memory data [Required] =====----------------------------------
          # Description: Data for LPDDR4/5 memory.
          lpddr_dmem: lpddr_dmem.bin
          # --------------------------===== LPDDR memory data for quick boot [Optional] =====---------------------------
          # Description: Data for LPDDR4/5 memory in quick boot.
          lpddr_dmem_qb: lpddr_dmem_qb.bin
          # -----------------------------------------===== OEI [Required] =====-----------------------------------------
          # Description: OEI - Optional Executable Image firmware
          oei_ddr: oei_ddr.bin
          # -----------------------------------===== Quick Boot Data [Optional] =====-----------------------------------
          # Description: QB data - Optional Quick boot data, if defined a new empty record will be added just behind DDR
          # FW entry
          qb_data: qb_data.bin

        #  ==== [Example of possible configuration: #2 OEI TCM Settings (ECC configuration etc.), erase if not used] ====
        # OEI TCM settings (ECC etc.)
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000001FFC0000
        # entry_point:                   0x000000001FFC0001
        # image_type:                    oei
        # core_id:                       cortex-m33
        # hash_type:                     SHA384
          # -------------------------------------===== OEI TCM FW [Required] =====--------------------------------------
          # Description: OEI(Optional Executable Image) TCM settings binary file.
          oei_tcm: oei_tcm.bin

        #  =============== [Example of possible configuration: #3 Boot system manager, erase if not used] ===============
        # System booting image
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000001FFC0000
        # image_type:                    executable
        # core_id:                       cortex-m33
        # hash_type:                     SHA384
          # ---------------------------------===== Boot system manager [Required] =====---------------------------------
          # Description: System manager booting image
          system_manager: system_manager.bin

        #  ======== [Example of possible configuration: #4 Cortex M7 additional application, erase if not used] =========
        # Cortex M7 additional application
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x00000000303C0000
        # entry_point:                   0x0000000000000000
        # image_type:                    executable
        # core_id:                       cortex-m7-1
        # meta_data_start_cpu_id:        1
        # hash_type:                     SHA384
          # --------------------------===== Cortex M7 additional application [Required] =====---------------------------
          # Description: Cortex M7 additional application
          cortex_m7_app: cortex_m7_app.bin

        #  ======================= [Example of possible configuration: #5 SPL, erase if not used] =======================
        # U-Boot SPL (Secondary program loader)
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x0000000020480000
        # image_type:                    executable
        # core_id:                       cortex-a55
        # meta_data_start_cpu_id:        2
        # hash_type:                     SHA384
          # -----------------------------------------===== SPL [Required] =====-----------------------------------------
          # Description: SPL firmware
          spl: spl.bin

        #  ==================== [Example of possible configuration: #6 V2X Dummy, erase if not used] ====================
        # V2X dummy image container definition
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000008B000000
        # image_type:                    v2x_dummy
        # core_id:                       cortex-m33
        # hash_type:                     SHA384
          # --------------------------------------===== V2X Dummy [Required] =====--------------------------------------
          # Description: If Present, V2X dummy image will be added to Image Array Entry (no data record)
          v2x_dummy: true

        #  ==================== [Example of possible configuration: #7 Uboot ATF, erase if not used] ====================
        # U-Boot ATF container definition
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000008A200000
        # image_type:                    executable
        # core_id:                       cortex-a55
        # meta_data_start_cpu_id:        2
        # hash_type:                     SHA384
          # -------------------------------------===== ATF binary [Required] =====--------------------------------------
          # Description: ARM Trusted Firmware binary file.
          atf: bl31.bin Define path to the ARM Trusted Firmware
        - atf: ./bl31-imx95.bin-optee
          is_encrypted: true

        #  ====================== [Example of possible configuration: #8 Uboot, erase if not used] ======================
        # U-Boot container definition
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x0000000090200000
        # image_type:                    executable
        # core_id:                       cortex-a55
        # meta_data_start_cpu_id:        2
        # hash_type:                     SHA384
          # ------------------------------------===== U-Boot binary [Required] =====------------------------------------
          # Description: U-Boot binary file.
          uboot: u-boot.bin Define path to the U-Boot binary file
        - uboot: ./u-boot_mx95_19x19.bin
          is_encrypted: true

        #  ======== [Example of possible configuration: #9 TEE Trusted Execution Environment, erase if not used] ========
        # A TEE (Trusted Execution Environment) is a trusted OS running in some secure environment, for example, TrustZone on ARM CPUs, or a separate secure co-processor etc. A TEE driver handles the details needed to communicate with the TEE.
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000008C000000
        # image_type:                    executable
        # core_id:                       cortex-a55
        # meta_data_start_cpu_id:        2
        # hash_type:                     SHA384
          # -----------------------------------------===== TEE [Required] =====-----------------------------------------
          # Description: TEE - Trusted Execution Environment binary
          tee: tee.bin Define path to the TEE (Trusted Execution Environment)
        - tee: ./tee.bin

        #  =============== [Example of possible configuration: #10 Linux Kernel Image, erase if not used] ===============
        # Linux kernel Image container definition
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x0000000090400000
        # image_type:                    executable
        # core_id:                       cortex-a55
        # meta_data_start_cpu_id:        2
        # hash_type:                     SHA384
          # ------------------------------===== Linux Kernel Image Binary [Required] =====------------------------------
          # Description: Linux kernel executable Image binary file (typically Image.bin)
          kernel: Image.bin

        #  ================ [Example of possible configuration: #11 Device Tree Blob, erase if not used] ================
        # Device Tree Blob (DTB) container definition
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x0000000093000000
        # entry_point:                   0x0000000000000000
        # image_type:                    data
        # core_id:                       cortex-a55
        # hash_type:                     SHA384
          # -------------------------------===== Device Tree Blob Binary [Required] =====-------------------------------
          # Description: Device Tree Blob (DTB) binary file containing hardware description
          dtb: device-tree.dtb

        #  ============== [Example of possible configuration: #12 General Image Entry, erase if not used] ===============
        # General Image Entry
          # -------------------------------------===== Image path [Optional] =====--------------------------------------
          # Description: Path to image binary (absolute/relative). In case that only Image Array entry without any data
          # image is needed, Just do not use the image path. In case that the image size in container should be aligned
          # differently then SPSDK do (4 bytes for ELE images, 1 byte otherwise), there is hidden option
          # 'image_size_alignment' where could be override image size by any custom value.
          image_path: my_image.bin
          # ---------------------------===== Image offset in AHAB container [Optional] =====----------------------------
          # Description: Offset in bytes from start of container header to beginning of the image. Zero value means
          # automatic placing the image with proper alignment after previous one, this is recommended for
          # serial_downloader mode. In case of XiP type of AHAB image, the load_address and entry_point must correspond
          # to this values. Example of setting of load_address - AHAB_IMAGE_ADDRESS+IMAGE_OFFSET=LOAD_ADDRESS. The
          # Booting core images must be located after the other ones
          image_offset: 0
          # ------------------------------===== Image destination address [Required] =====------------------------------
          # Description: Address the image is written to in memory (absolute address in system memory).
          load_address: '0x1FFC_0000'
          # ----------------------------------===== Image entry point [Required] =====----------------------------------
          # Description: Image entry point (absolute address). Valid only for executable image types.
          entry_point: '0x1FFC_0000'
          # -------------------------------------===== Image type [Required] =====--------------------------------------
          # Description: Kind of image.
          # Possible options: 
          # executable_fast_boot_image, oei_ddr, v2x_dummy, ele_as_image, ele, v2x_as_image, v2x_primary, v2x_secondary,
          # v2x_rom_patch>
          image_type: executable
          # ---------------------------------------===== Core ID [Required] =====---------------------------------------
          # Description: Defines the core the image is dedicated for. Not all cores are supported for all families.
          # Possible options: 
          core_id: dummy
          # ----------------------------------===== Image encryption [Optional] =====-----------------------------------
          # Description: Determines, whether image is encrypted or not.
          is_encrypted: false Set true for each image you want to encrypt
          is_encrypted: true
          # -------------------------------------===== Boot flags [Optional] =====--------------------------------------
          # Description: Boot flags controlling SCFW boot.
          boot_flags: 0
          # ------------------------------------===== Start CPU ID [Optional] =====-------------------------------------
          # Description: Resource ID of CPU to be started
          meta_data_start_cpu_id: 0
          # ------------------------------===== CPU memory unit start ID [Optional] =====-------------------------------
          # Description: Resource ID of the MU associated with the CPU
          meta_data_mu_cpu_id: 0
          # ---------------------------------===== Start partition ID [Optional] =====----------------------------------
          # Description: Partition ID of the partition to start
          meta_data_start_partition_id: 0
          # ----------------------------------===== Images HASH type [Optional] =====-----------------------------------
          # Description: HASH type of image.
          # Possible options: 
          hash_type: sha512

      # ================================================================================================================
      #                                      == Configuration of AHAB SRK table ==                                      
      # ================================================================================================================
      # ---------------------------------===== SRK Table [Conditionally required] =====---------------------------------
      # Description: SRK (Super Root key) table definition.
      srk_table: All attributes related to the signing
        # ----------------------------------------===== CA Flag [Optional] =====----------------------------------------
        # Description: CA Flag is used by HAB to indicate if the SRK is allowed to sign other keys. In AHAB CA Flag only
        # affects the final SRKH (Super Root Key Hash) value burned into chip fuses. It is not used in the AHAB signing
        # process itself. This option exists only for compatibility with systems where fuses are already programmed. In
        # most cases, this should remain false.
        flag_ca: false
        # ------------------------------------===== Hash Algorithm [Optional] =====-------------------------------------
        # Description: Hash algorithm used for SRK records. If not specified, default algorithm based on key type will
        # be used.
        # Possible options: 
        # shake_256_512, sm3>
        hash_algorithm: default
        hash_algorithm: sha3_512
        # ------------------------------===== Super Root Key (SRK) table [Required] =====-------------------------------
        # Description: Table containing the used SRK records. All SRKs must be of the same type. Supported signing
        # algorithms are: RSA-PSS, ECDSA, Dilithium or SM2. Supported hash algorithms: sha256, sha384, sha512, sha3_256,
        # sha3_384, sha3_512, sm3. Supported key sizes/curves: prime256v1, sec384r1, sec512r1, rsa2048, rsa4096,
        # dilithium3, sm2. Certificate may be of Certificate Authority. Dilithium algorithms are supported just in new
        # type of AHAB container
        srk_array:
          - my_srk_public_key0.pub
          - my_srk_public_key1.pub
          - my_srk_public_key2.pub
          - my_srk_public_key3.pub
          - ../../../_data/keys/ecc521/srk0_ecc521.pub
          - ../../../_data/keys/ecc521/srk1_ecc521.pub
          - ../../../_data/keys/ecc521/srk2_ecc521.pub
          - ../../../_data/keys/ecc521/srk3_ecc521.pub

        # ==============================================================================================================
        #               == Configuration of AHAB SRK table in case that the double signing (ECC + PQC) ==               
        # ==============================================================================================================
        # -----------------------------------===== Second SRK Table [Optional] =====------------------------------------
        srk_table_#2:
          # ---------------------------------------===== CA Flag [Optional] =====---------------------------------------
          # Description: CA Flag is used by AHAB to indicate if the SRK is allowed to sign other keys. In AHAB CA Flag
          # only affects the final SRKH (Super Root Key Hash) value burned into chip fuses. It is not used in the AHAB
          # signing process itself. This option exists only for compatibility with systems where fuses are already
          # programmed. In most cases, this should remain false.
          flag_ca: false
          # -----------------------------------===== Hash Algorithm [Optional] =====------------------------------------
          # Description: Hash algorithm used for SRK records. If not specified, default algorithm based on key type will
          # be used.
          # Possible options: 
          # shake_256_512, sm3>
          hash_algorithm: default
          hash_algorithm: sha3_512
          # -----------------------------===== Super Root Key (SRK) table [Required] =====------------------------------
          # Description: Table containing the used SRK Dilithium records. All SRKs must be of the same type. Supported
          # signing algorithms are: Dilithium level 3. Supported hash algorithms: sha3_256, sha3_384, sha3_512.
          # Certificate may be of Certificate Authority.
          srk_array:
            - my_srk_public_key0.pub
            - my_srk_public_key1.pub
            - my_srk_public_key2.pub
            - my_srk_public_key3.pub
            - ../../../_data/keys/mldsa65/srk0_mldsa65.pub
            - ../../../_data/keys/mldsa65/srk1_mldsa65.pub
            - ../../../_data/keys/mldsa65/srk2_mldsa65.pub
            - ../../../_data/keys/mldsa65/srk3_mldsa65.pub

      # ================================================================================================================
      #           == Optional configuration of AHAB Container Certificate (if not used, erase the section) ==           
      # ================================================================================================================
      # ----------------------------------===== The AHAB certificate [Optional] =====-----------------------------------
      # Description: The file that contains AHAB certificate. It could be used already prepared binary form signed by
      # SRK, or it is possible to use configuration YAML file of certificate and the AHAB export process it will export
      # it itself.
      certificate: my_ahab_certificate.bin

      # ================================================================================================================
      #         == Optional configuration of AHAB Container Encryption blob (if not used, erase the section) ==         
      # ================================================================================================================
      # -------------------------------------===== Encryption blob [Optional] =====-------------------------------------
      # Description: Encryption blob container definition
      blob:
        blob:
        # ------------------------------------===== Key identifier [Required] =====-------------------------------------
        # Description: The key identifier that has been used to generate DEK keyblob.
        key_identifier: 0 All attributes related to the encrypting
          key_identifier: 2
        # -------------------------------------===== DEK key size [Required] =====--------------------------------------
        # Description: Data Encryption key size. Used for AES CBC-MAC (128/192/256 size)
        # Possible options: <128, 192, 256>
        dek_key_size: 128
          dek_key_size: 128
        # ----------------------------------------===== DEK key [Required] =====----------------------------------------
        # Description: Data Encryption key. Used for AES CBC-MAC (128/192/256 size). The HEX format is accepted
        dek_key: my_dek_key.txt
          dek_key: ../../../_data/keys/dek_key.txt
        # --------------------------------------===== DEK keyblob [Optional] =====--------------------------------------
        # Description: Wrapped Data Encryption key. Used for AES CBC-MAC (128/192/256 size). The HEX format is accepted.
        # If NOT used, the empty keyblob is inserted into container and need to be updated later.
        dek_keyblob: my_wrapped_key.txt
          dek_keyblob: ./outputs/dek_keyblob.bin

# Copyright 2025 NXP
#
# SPDX-License-Identifier: BSD-3-Clause
# ==========================  Advanced High-Assurance Boot Configuration template for mimx9596.  ===========================

# ======================================================================================================================
#                                                 == General Options ==
# ======================================================================================================================
# ------------------------------------------===== MCU family [Required] =====-------------------------------------------
# Description: Family identifier including the chip revision. If revision is not present, latest revision is used as
# default.
# Possible options: 
family: mimx9596
# -----------------------------------------===== MCU revision [Optional] =====------------------------------------------
# Description: Revision of silicon
revision: latest IMPORTANT! Revision B0 has different container format than A1
# ----------------------------------===== Target memory [Conditionally required] =====----------------------------------
# Description: Target memory for AHAB container
# Possible options: 
target_memory: standard
# ---------------------------------------===== Output file name [Required] =====----------------------------------------
# Description: Output AHAB file name
output: ../outputs/secondary_encrypted_ahab.bin
# ---------------------------------------===== Container version [Optional] =====---------------------------------------
# Description: Force container version, if not specified the default version is used. This configuration option is valid
# only for chips that supports both AHAB container versions. Possible options <2, 1>
container_version: 2
# ------------------------------===== List of containers present in AHAB [Required] =====-------------------------------
# Description: The order of containers in the list defines the order in AHAB.
containers:
  - # --------------------------------------===== AHAB Container [Required] =====---------------------------------------
    # Description: Configurable Container format to add to AHAB image. This allow to configure all aspects of the AHAB
    # container.
    container:
      # --------------------------------===== Super Root Key (SRK) set [Required] =====---------------------------------
      # Description: Defines which set is used to authenticate the container.
      # Possible options: 
      srk_set: oem Define set is used to authenticate the container
      # ---------------------------------===== Used SRK [Conditionally required] =====----------------------------------
      # Description: Which key from SRK set is being used.
      used_srk_id: 0
      # -------------------------------------===== SRK revoke mask [Optional] =====-------------------------------------
      # Description: Bit-mask to indicate which SRKs to revoke. Bit set to 1 means revoke key. Bit 0 = revoke SRK_0, bit
      # 1 = revoke SRK_1 etc. Example of revocation SRK_0 and SRK_1 - the value should be 0x03
      srk_revoke_mask: "0x00"
      # ----------------------------------===== GDET runtime behavior [Optional] =====----------------------------------
      # Description: This option defines runtime behavior of Glitch detector. Not supported by all devices and their ELE
      # firmware.
      #  - disabled:       GDET is disabled after the first OEM container has been authenticated (default behavior)
      #  - enabled_eleapi: Automatically enable GDET during all ELE API calls
      #  - enabled:        Leave GDET enabled
      # Possible options: 
      gdet_runtime_behavior: disabled
      # ----------------------------------===== Check all signatures [Optional] =====-----------------------------------
      # Description: This option overrides a fuse to select verification mode.
      #  - default: Apply default fuse policy.
      #  - check_all_signatures: Force verification of all present signatures.
      # Possible options: 
      check_all_signatures: check_all_signatures
      # ----------------------------------------===== Fast boot [Optional] =====----------------------------------------
      # Description: This option enables fast boot mode.
      #  - disabled: Fast boot disabled.
      #  - hash_and_copy: ELE will do the hash and copy (when disabled, BootROM will do the copy).
      #  - external_accelerator: Use external accelerator for authentication (e.g. V2X on i.MX95B0, i.MX943 and
      # i.MX952).
      #  - hash_and_copy_with_external_accelerator:ELE will do hash and copy, and use external accelerator for
      # authentication.
      # Possible options: 
      fast_boot: disabled
      # --------------------------------------===== Fuse version [Optional] =====---------------------------------------
      # Description: The value must be equal or greater than the version stored in fuses to allow loading this
      # container.
      fuse_version: 0
      # ------------------------------------===== Software version [Optional] =====-------------------------------------
      # Description: Number used by Privileged Host Boot Companion (PHBC) to select between multiple images with same
      # Fuse version field.
      sw_version: 0
      # -------------------------------===== AHAB container signing key [Optional] =====--------------------------------
      # Description: Private key used for sign the container header. Header can be signed by SRK. The referenced SRK
      # must not have been revoked.
      signer: ../../../_data/keys/ecc521/srk0_ecc521.pem
      # ------------------===== AHAB container signer for second signature (PQC only) [Optional] =====------------------
      # Description: Signature provider configuration in format 'type=;=;=' or a
      # private key used for second sign (PQC only) of the container header. Header can be signed by SRK. The referenced
      # SRK must not have been revoked.
      signer_#2: ../../../_data/keys/mldsa65/srk0_mldsa65.pem

      # ================================================================================================================
      #                     == Configuration of AHAB Container images (array of multiple images) ==
      # ================================================================================================================
      # ---------------------------------------===== Image array [Required] =====---------------------------------------
      # Description: Array of image entries.
      images:
          # U-Boot ATF container definition
          # Image array default settings. Can be override by defines that are hidden in template:
          # load_address:                  0x000000008A200000
          # image_type:                    executable
          # core_id:                       cortex-a55
          # meta_data_start_cpu_id:        2
          # hash_type:                     SHA384
          # -------------------------------------===== ATF binary [Required] =====--------------------------------------
          # Description: ARM Trusted Firmware binary file.
        - atf: ./bl31-imx95.bin-optee Define path to the ARM Trusted Firmware
          is_encrypted: true Set true for each image you want to encrypt

          # U-Boot container definition
          # Image array default settings. Can be override by defines that are hidden in template:
          # load_address:                  0x0000000090200000
          # image_type:                    executable
          # core_id:                       cortex-a55
          # meta_data_start_cpu_id:        2
          # hash_type:                     SHA384
          # ------------------------------------===== U-Boot binary [Required] =====------------------------------------
          # Description: U-Boot binary file.
        - uboot: ./u-boot_mx95_19x19.bin Define path to the U-Boot binary file
          is_encrypted: true Set true for each image you want to encrypt

          # A TEE (Trusted Execution Environment) is a trusted OS running in some secure environment, for example, TrustZone on ARM CPUs, or a separate secure co-processor etc. A TEE driver handles the details needed to communicate with the TEE.
          # Image array default settings. Can be override by defines that are hidden in template:
          # load_address:                  0x000000008C000000
          # image_type:                    executable
          # core_id:                       cortex-a55
          # meta_data_start_cpu_id:        2
          # hash_type:                     SHA384
          # -----------------------------------------===== TEE [Required] =====-----------------------------------------
          # Description: TEE - Trusted Execution Environment binary
        - tee: ./tee.bin Define path to the TEE (Trusted Execution Environment)
          is_encrypted: true Set true for each image you want to encrypt

      # ================================================================================================================
      #                                      == Configuration of AHAB SRK table ==
      # ================================================================================================================
      # ---------------------------------===== SRK Table [Conditionally required] =====---------------------------------
      # Description: SRK (Super Root key) table definition.
      srk_table: All attributes related to the signing
        # ----------------------------------------===== CA Flag [Optional] =====----------------------------------------
        # Description: CA Flag is used by HAB to indicate if the SRK is allowed to sign other keys
        flag_ca: false
        # -----------------------------------===== Hash Algorithm [Optional] =====------------------------------------
        # Description: Hash algorithm used for SRK records. If not specified, default algorithm based on key type will
        # be used.
        # Possible options: 
        hash_algorithm: sha3_512
        # ------------------------------===== Super Root Key (SRK) table [Required] =====-------------------------------
        # Description: Table containing the used SRK records. All SRKs must be of the same type. Supported signing
        # algorithms are: RSA-PSS, ECDSA, Dilithium or SM2. Supported hash algorithms: sha256, sha384, sha512, sha3_256,
        # sha3_384, sha3_512, sm3. Supported key sizes/curves: prime256v1, sec384r1, sec512r1, rsa2048, rsa4096,
        # dilithium3, sm2. Certificate may be of Certificate Authority. Dilithium algorithms are supported just in new
        # type of AHAB container
        srk_array:
          - ../../../_data/keys/ecc521/srk0_ecc521.pub
          - ../../../_data/keys/ecc521/srk1_ecc521.pub
          - ../../../_data/keys/ecc521/srk2_ecc521.pub
          - ../../../_data/keys/ecc521/srk3_ecc521.pub

        # ==============================================================================================================
        #               == Configuration of AHAB SRK table in case that the double signing (ECC + PQC) ==               
        # ==============================================================================================================
        # -----------------------------------===== Second SRK Table [Optional] =====------------------------------------
        srk_table_#2:
          # ---------------------------------------===== CA Flag [Optional] =====---------------------------------------
          # Description: CA Flag is used by AHAB to indicate if the SRK is allowed to sign other keys. In AHAB CA Flag
          # only affects the final SRKH (Super Root Key Hash) value burned into chip fuses. It is not used in the AHAB
          # signing process itself. This option exists only for compatibility with systems where fuses are already
          # programmed. In most cases, this should remain false.
          flag_ca: false
          # -----------------------------------===== Hash Algorithm [Optional] =====------------------------------------
          # Description: Hash algorithm used for SRK records. If not specified, default algorithm based on key type will
          # be used.
          # Possible options: 
          hash_algorithm: sha3_512
          # -----------------------------===== Super Root Key (SRK) table [Required] =====------------------------------
          # Description: Table containing the used SRK Dilithium records. All SRKs must be of the same type. Supported
          # signing algorithms are: Dilithium level 3. Supported hash algorithms: sha3_256, sha3_384, sha3_512.
          # Certificate may be of Certificate Authority.
          srk_array:
            - ../../../_data/keys/mldsa65/srk0_mldsa65.pub
            - ../../../_data/keys/mldsa65/srk1_mldsa65.pub
            - ../../../_data/keys/mldsa65/srk2_mldsa65.pub
            - ../../../_data/keys/mldsa65/srk3_mldsa65.pub

        # ================================================================================================================
        #         == Optional configuration of AHAB Container Encryption blob (if not used, erase the section) ==         
        # ================================================================================================================
        # -------------------------------------===== Encryption blob [Optional] =====-------------------------------------
        # Description: Encryption blob container definition
        blob:
          # ------------------------------------===== Key identifier [Required] =====-------------------------------------
          # Description: The key identifier that has been used to generate DEK keyblob.
          key_identifier: 2 All attributes related to the encrypting
          # -------------------------------------===== DEK key size [Required] =====--------------------------------------
          # Description: Data Encryption key size. Used for AES CBC-MAC (128/192/256 size)
          # Possible options: <128, 192, 256>
          dek_key_size: 128
          # ----------------------------------------===== DEK key [Required] =====----------------------------------------
          # Description: Data Encryption key. Used for AES CBC-MAC (128/192/256 size). The HEX format is accepted
          dek_key: ../../../_data/keys/dek_key.txt
          # --------------------------------------===== DEK keyblob [Optional] =====--------------------------------------
          # Description: Wrapped Data Encryption key. Used for AES CBC-MAC (128/192/256 size). The HEX format is accepted.
          # If NOT used, the empty keyblob is inserted into container and need to be updated later.
          dek_keyblob: ./outputs/dek_keyblob.bin

3.6 Exporting of full AHAB image (container set)

U-Boot image consists from two image container sets. The first one contains ELE firmware, DDR firmware with OEI, system manager and U-Boot SPL. This image is loaded using the SDPS protocol. Once the U-Boot SPL is loaded to OCRAM the fastboot is opened and the second container is loaded using the fastboot protocol.

If the image is intended for loading using the UUU, the memory type should be set to serial_downloader. However the type of each individual AHAB should be set to standard, because it will be stored in flash memory.

nxpimage -v bootable-image export -c u-boot-flash_template.yaml -o flash.bin

YamlDiffWidget("inputs/mx95_encrypted_ahab_bimg.diffc").html

nxpimage bootable-image get-templates -f mimx9596 -o workspace --force 
Creating workspace/bootimg_mimx9596_serial_downloader.yaml template file.
Creating workspace/bootimg_mimx9596_flexspi_nor.yaml template file.
Creating workspace/bootimg_mimx9596_emmc.yaml template file.
Creating workspace/bootimg_mimx9596_sd.yaml template file.
Creating workspace/bootimg_mimx9596_recovery_spi.yaml template file.

Configuration Differences

Show Diff Download Config

# =================  Bootable Image Configuration for mimx9596, Revision: latest / Serial downloader.  =================

# ======================================================================================================================
#                                                 == General Options ==                                                 
# ======================================================================================================================
# -------------------------------------===== The chip family name [Required] =====--------------------------------------
# Description: NXP chip family identifier.
family: mimx9596
# -----------------------------------------===== MCU revision [Optional] =====------------------------------------------
# Description: Revision of silicon. The 'latest' name, means most current revision.
# Possible options: 
revision: latest
# ------------------------------------------===== Memory type [Required] =====------------------------------------------
# Description: Specify type of memory used by bootable image description.
memory_type: serial_downloader
# ----------------------------------------===== Initial segment [Optional] =====----------------------------------------
# Description: The segment name or the index of initial segment in exported image
init_offset: 0
# -------------------------------===== Path to directory for post export [Optional] =====-------------------------------
# Description: Path to directory where post export artifacts like fuse scripts, keyblobs etc. will be exported
post_export: output path to the directory where fuse scripts will be saved
post_export: ./outputs/post_export
# ======================================================================================================================
#                                      == Primary Executable Segment definition ==                                      
# ======================================================================================================================
# ----------------------------------===== Primary Image Container Set [Optional] =====----------------------------------
# Description: This is primary Image Container Set that is validated by ROM and usually contains DDR initialization and
# SPL code. It could be used as pre-prepared binary form of AHAB and also YAML configuration file for AHAB. In case that
# YAML configuration file is used, the Bootable image tool build the AHAB itself.
primary_image_container_set: primary_image_container_set.yaml path to our signed primary container set configuration/binary
primary_image_container_set: ../outputs/primary_encrypted_ahab.bin
# ======================================================================================================================
#                                     == Secondary Executable Segment definition ==                                     
# ======================================================================================================================
secondary_image_container_set: secondary_image_container_set.yaml path to our signed secondary container set configuration/binary
secondary_image_container_set: ../outputs/secondary_encrypted_ahab.bin

# Copyright 2025 NXP
#
# SPDX-License-Identifier: BSD-3-Clause
# =======================  Bootable Image Configuration template for mimx9596 / serial_downloader.  ========================

# ======================================================================================================================
#                                                 == General Options ==
# ======================================================================================================================
# ------------------------------------------===== MCU family [Required] =====-------------------------------------------
# Description: MCU family name.
family: mimx9596
# -------------------------------------===== Chip silicon revision [Optional] =====-------------------------------------
# Description: If needed this could be used to specify silicon revision of device.
# Possible options: 
revision: latest
# ------------------------------------------===== Memory type [Required] =====------------------------------------------
# Description: Specify type of memory used by bootable image description.
memory_type: serial_downloader
# ----------------------------------------===== Initial segment [Optional] =====----------------------------------------
# Description: The segment name or the index of initial segment in exported image
init_offset: 0
# -------------------------------===== Path to directory for post export [Optional] =====-------------------------------
# Description: Path to directory where post export artifacts like fuse scripts, keyblobs etc. will be exported
post_export: ./outputs/post_export path to the directory where fuse scripts will be saved
# ======================================================================================================================
#                                      == Primary executable Segment definition ==
# ======================================================================================================================
# ------------------------------------===== Primary AHAB container [Optional] =====-------------------------------------
# Description: This is primary AHAB image that is validated by ROM and usually contains DDR initialization and SPL code.
# AHAB container image path. It could be used as pre-prepared binary form of AHAB and also YAML configuration file for
# AHAB. In case that YAML configuration file is used, the Bootable image tool build the AHAB itself.
primary_image_container_set: ../outputs/primary_encrypted_ahab.bin path to our signed primary container set configuration/binary
# ======================================================================================================================
#                                     == Secondary executable Segment definition ==
# ======================================================================================================================
# -----------------------------------===== Secondary AHAB container [Optional] =====------------------------------------
# Description: This is secondary AHAB image that is validated by SPL from primary image. AHAB container image path. It
# could be used as pre-prepared binary form of AHAB and also YAML configuration file for AHAB. In case that YAML
# configuration file is used, the Bootable image tool build the AHAB itself.
secondary_image_container_set: ../outputs/secondary_encrypted_ahab.bin path to our signed secondary container set
configuration/binary

U_BOOT_FLASH_BOOT_CFG = "inputs/bootimg_encrypted_mx95_serial_downloader.yaml"
U_BOOT_FLASH_BOOT = "outputs/flash.bin"

VERBOSITY = "-v"

# EXPORT FULL U-BOOT IMAGE
%! nxpimage $VERBOSITY bootable-image export --config $U_BOOT_FLASH_BOOT_CFG --output $U_BOOT_FLASH_BOOT

nxpimage -v bootable-image export --config inputs/bootimg_encrypted_mx95_serial_downloader.yaml --output outputs/flash.bin 
INFO:spsdk.apps.nxpimage_apps.nxpimage_bimg:Created Bootable Image:
Name:      Bootable Image for mimx9596, Revision: latest
Starts:    0x0
Ends:      0x291fff
Size:      Size: 2.6 MiB; 2,695,168 B
Alignment: 1 B
Execution Start Address: Not defined
Pattern:zeros
Memory type: MemoryType.SERIAL_DOWNLOADER

INFO:spsdk.apps.nxpimage_apps.nxpimage_bimg:Created Bootable Image memory map:

+==0x0000_0000= Bootable Image for mimx9596, Revision: latest ===+
|                   Size: 2.6 MiB; 2,695,168 B                   |
|           Memory type: MemoryType.SERIAL_DOWNLOADER            |
|                         Pattern: zeros                         |
|+==0x0000_0000= primary_image_container_set ===================+|
||                  Size: 894.0 kiB; 915,456 B                  ||
||          AHAB Image for mimx9596, Revision: latest           ||
||                        Pattern: zeros                        ||
||+==0x0000_0000= AHAB Containers =============================+||
|||                  Size: 48.0 kiB; 49,152 B                  |||
|||                   AHAB Containers block                    |||
|||                       Pattern: zeros                       |||
|||+==0x0000_0000= AHAB Container 0 ==========================+|||
||||                  Size: 8.0 kiB; 8,227 B                  ||||
||||              AHAB Container for nxp_SWver:0              ||||
|||+==0x0000_2022=============================================+|||
|||                        Gap: 8.0 kiB                        |||
|||+==0x0000_4000= AHAB Container 1 ==========================+|||
||||                       Size: 832 B                        ||||
||||              AHAB Container for nxp_SWver:0              ||||
|||+==0x0000_433f=============================================+|||
|||                       Gap: 15.2 kiB                        |||
|||+==0x0000_8000= AHAB Container 2 ==========================+|||
||||                  Size: 7.0 kiB; 7,181 B                  ||||
||||              AHAB Container for oem_SWver:0              ||||
|||+==0x0000_9c0c=============================================+|||
||+==0x0000_bfff===============================================+||
||+==0x0000_c000= Container 0 AHAB Data Image 0 ===============+||
|||                  Size: 44.6 kiB; 45,648 B                  |||
||| AHAB encrypted data block for ele core and ele Image Type. |||
||+==0x0001_724f===============================================+||
||                         Gap: 3.4 kiB                         ||
||+==0x0001_8000= Container 1 AHAB Data Image 0 ===============+||
|||                  Size: 63.8 kiB; 65,280 B                  |||
|||  AHAB encrypted data block for v2x-1 core and v2x_primary  |||
|||                        Image Type.                         |||
||+==0x0002_7eff===============================================+||
||                          Gap: 256 B                          ||
||+==0x0002_8000= Container 1 AHAB Data Image 1 ===============+||
|||                  Size: 28.0 kiB; 28,672 B                  |||
||| AHAB encrypted data block for v2x-2 core and v2x_secondary |||
|||                        Image Type.                         |||
||+==0x0002_efff===============================================+||
||+==0x0002_f000= OEI DDR =====================================+||
|||                 Size: 316.0 kiB; 323,584 B                 |||
|||AHAB encrypted data block for cortex-m33 core and oei Image |||
|||                           Type.                            |||
||+==0x0007_dfff===============================================+||
||+==0x0007_e000= OEI DDR =====================================+||
|||                         Size: 0 B                          |||
|||   AHAB data block for dummy core and oei_ddr Image Type.   |||
||+==0x0007_dfff===============================================+||
||                        Gap: 64.0 kiB                         ||
||+==0x0008_e000= OEI TCM =====================================+||
|||                   Size: 5.0 kiB; 5,120 B                   |||
|||AHAB encrypted data block for cortex-m33 core and oei Image |||
|||                           Type.                            |||
||+==0x0008_f3ff===============================================+||
||+==0x0008_f400= System manager ==============================+||
|||                 Size: 163.0 kiB; 166,912 B                 |||
|||AHAB encrypted data block for cortex-m33 core and executable|||
|||                        Image Type.                         |||
||+==0x000b_7fff===============================================+||
||+==0x000b_8000= Additional Cortex M7 application ============+||
|||                  Size: 13.0 kiB; 13,312 B                  |||
|||     AHAB encrypted data block for cortex-m7-1 core and     |||
|||                   executable Image Type.                   |||
||+==0x000b_b3ff===============================================+||
||+==0x000b_b400= U-Boot SPL ==================================+||
|||                 Size: 145.0 kiB; 148,480 B                 |||
|||AHAB encrypted data block for cortex-a55 core and executable|||
|||                        Image Type.                         |||
||+==0x000d_f7ff===============================================+||
||+==0x000d_f800= V2X core Dummy record =======================+||
|||                         Size: 0 B                          |||
|||AHAB encrypted data block for cortex-m33 core and v2x_dummy |||
|||                        Image Type.                         |||
||+==0x000d_f7ff===============================================+||
|+==0x000d_f7ff=================================================+|
|+==0x000d_f800= secondary_image_container_set =================+|
||                  Size: 1.7 MiB; 1,779,712 B                  ||
||          AHAB Image for mimx9596, Revision: latest           ||
||                        Pattern: zeros                        ||
||+==0x000d_f800= AHAB Containers =============================+||
|||                  Size: 48.0 kiB; 49,152 B                  |||
|||                   AHAB Containers block                    |||
|||                       Pattern: zeros                       |||
|||+==0x000d_f800= AHAB Container 0 ==========================+|||
||||                  Size: 6.5 kiB; 6,669 B                  ||||
||||              AHAB Container for oem_SWver:0              ||||
|||+==0x000e_120c=============================================+|||
||+==0x000e_b7ff===============================================+||
||+==0x000e_b800= ATF - ARM Trusted Firmware ==================+||
|||                  Size: 38.0 kiB; 38,912 B                  |||
|||AHAB encrypted data block for cortex-a55 core and executable|||
|||                        Image Type.                         |||
||+==0x000f_4fff===============================================+||
||+==0x000f_5000= U-Boot Firmware =============================+||
|||                 Size: 1.0 MiB; 1,097,728 B                 |||
|||AHAB encrypted data block for cortex-a55 core and executable|||
|||                        Image Type.                         |||
||+==0x0020_0fff===============================================+||
||+==0x0020_1000= U-Boot TEE - Trusted Execution Environment ==+||
|||                 Size: 580.0 kiB; 593,920 B                 |||
|||AHAB encrypted data block for cortex-a55 core and executable|||
|||                        Image Type.                         |||
||+==0x0029_1fff===============================================+||
|+==0x0029_1fff=================================================+|
+==0x0029_1fff===================================================+

Success. (Bootable Image: outputs/flash.bin created) 
INFO:spsdk.image.ahab.ahab_container:Generated file containing SRK hash: outputs/post_export/ahab_oem2_srk0_hash.txt
INFO:spsdk.image.ahab.ahab_container:
Fuses info:

 --== Grouped register name: SRKH ==-- 
OTP ID: 128, Value: 0x241CF233
OTP ID: 129, Value: 0x598B9EEF
OTP ID: 130, Value: 0xDB555149
OTP ID: 131, Value: 0x11CA4D90
OTP ID: 132, Value: 0xADD4F20D
OTP ID: 133, Value: 0xA595873D
OTP ID: 134, Value: 0xD6BF1611
OTP ID: 135, Value: 0xA9F8BAA6
OTP ID: 136, Value: 0x6E3413DC
OTP ID: 137, Value: 0x1923841E
OTP ID: 138, Value: 0x10D0A7C0
OTP ID: 139, Value: 0xDBAEC7B4
OTP ID: 140, Value: 0xCA74C2A2
OTP ID: 141, Value: 0x358BC459
OTP ID: 142, Value: 0xB2997934
OTP ID: 143, Value: 0xF1CA7902

INFO:spsdk.image.ahab.ahab_container:Generated script for writing fuses for container 2: outputs/post_export/ahab_oem2_srk0_hash_nxpele.bcf
INFO:spsdk.image.ahab.ahab_container:Generated file containing SRK hash: outputs/post_export/ahab_oem2_srk1_hash.txt
INFO:spsdk.image.ahab.ahab_container:
Fuses info:

 --== Grouped register name: PQC_SRKH ==-- 
OTP ID: 448, Value: 0xA4C25CF9
OTP ID: 449, Value: 0x3A897E6B
OTP ID: 450, Value: 0x65B02428
OTP ID: 451, Value: 0x97674462
OTP ID: 452, Value: 0xBF41C13A
OTP ID: 453, Value: 0x86D9F03A
OTP ID: 454, Value: 0x2EF246AE
OTP ID: 455, Value: 0x7A347919
OTP ID: 456, Value: 0x555B5447
OTP ID: 457, Value: 0xE801DF23
OTP ID: 458, Value: 0x7C278F6D
OTP ID: 459, Value: 0xC8FBEA31
OTP ID: 460, Value: 0x76CA9A8E
OTP ID: 461, Value: 0x3CE47C57
OTP ID: 462, Value: 0x640A8572
OTP ID: 463, Value: 0x09ACB465

INFO:spsdk.image.ahab.ahab_container:Generated script for writing fuses for container 2: outputs/post_export/ahab_oem2_srk1_hash_nxpele.bcf
INFO:spsdk.image.ahab.ahab_container:Generated file containing SRK hash: outputs/post_export/ahab_oem0_srk0_hash.txt
INFO:spsdk.image.ahab.ahab_container:
Fuses info:

 --== Grouped register name: SRKH ==-- 
OTP ID: 128, Value: 0x241CF233
OTP ID: 129, Value: 0x598B9EEF
OTP ID: 130, Value: 0xDB555149
OTP ID: 131, Value: 0x11CA4D90
OTP ID: 132, Value: 0xADD4F20D
OTP ID: 133, Value: 0xA595873D
OTP ID: 134, Value: 0xD6BF1611
OTP ID: 135, Value: 0xA9F8BAA6
OTP ID: 136, Value: 0x6E3413DC
OTP ID: 137, Value: 0x1923841E
OTP ID: 138, Value: 0x10D0A7C0
OTP ID: 139, Value: 0xDBAEC7B4
OTP ID: 140, Value: 0xCA74C2A2
OTP ID: 141, Value: 0x358BC459
OTP ID: 142, Value: 0xB2997934
OTP ID: 143, Value: 0xF1CA7902

INFO:spsdk.image.ahab.ahab_container:Generated script for writing fuses for container 0: outputs/post_export/ahab_oem0_srk0_hash_nxpele.bcf
INFO:spsdk.image.ahab.ahab_container:Generated file containing SRK hash: outputs/post_export/ahab_oem0_srk1_hash.txt
INFO:spsdk.image.ahab.ahab_container:
Fuses info:

 --== Grouped register name: PQC_SRKH ==-- 
OTP ID: 448, Value: 0xA4C25CF9
OTP ID: 449, Value: 0x3A897E6B
OTP ID: 450, Value: 0x65B02428
OTP ID: 451, Value: 0x97674462
OTP ID: 452, Value: 0xBF41C13A
OTP ID: 453, Value: 0x86D9F03A
OTP ID: 454, Value: 0x2EF246AE
OTP ID: 455, Value: 0x7A347919
OTP ID: 456, Value: 0x555B5447
OTP ID: 457, Value: 0xE801DF23
OTP ID: 458, Value: 0x7C278F6D
OTP ID: 459, Value: 0xC8FBEA31
OTP ID: 460, Value: 0x76CA9A8E
OTP ID: 461, Value: 0x3CE47C57
OTP ID: 462, Value: 0x640A8572
OTP ID: 463, Value: 0x09ACB465

INFO:spsdk.image.ahab.ahab_container:Generated script for writing fuses for container 0: outputs/post_export/ahab_oem0_srk1_hash_nxpele.bcf
Performing post export
outputs/post_export/ahab_oem2_srk0_hash.txt
outputs/post_export/ahab_oem2_srk0_hash_nxpele.bcf
outputs/post_export/ahab_oem2_srk1_hash.txt
outputs/post_export/ahab_oem2_srk1_hash_nxpele.bcf
outputs/post_export/ahab_oem0_srk0_hash.txt
outputs/post_export/ahab_oem0_srk0_hash_nxpele.bcf
outputs/post_export/ahab_oem0_srk1_hash.txt
outputs/post_export/ahab_oem0_srk1_hash_nxpele.bcf

4. Download image

4.1 Download AHAB image

Set the boot mode to Cortex-M Serial Downloader (1001 on EVK boot switch) and download the files using the UUU tool

%! nxpuuu $VERBOSITY write --family mimx9596 --boot-device emmc $U_BOOT_FLASH_BOOT

nxpuuu -v write --family mimx9596 --boot-device emmc outputs/flash.bin 
SDPS: boot -f outputs/flash.bin


SDPV: write -f outputs/flash.bin -skipspl


SDPV: jump


Success

5. Write fuses

NOTE: For more information about fuses, refer to i.MX 95 signed AHAB with U-BOOT Jupyter Notebook.

6. Boot and test

Now change the boot mode to Cortex-M eMMC (1010 on EVK boot switch) and reset the board. Find the serial port that belongs to U-Boot console and interrupt the boot. When the console is switched to U-Boot menu, we can use the nxpele tool to communicate with the ELE.

%! nxpele --family mimx9596 --port COM266 --device uboot_serial get-info

nxpele --family mimx9596 --port COM266 --device uboot_serial get-info 
ELE get info ends successfully:
Command:              0xda
Version:              3
Length:               256
SoC ID:               MX95 - 0x9500
SoC version:          B000
Life Cycle:           OEM_CLSD - 0x0040
SSSM state:           4
Attest API version:   0
UUID:                 c9d88ddf5ace444da168dd2a520630e1
SHA256 ROM PATCH:     72d02b666a524aca0a3162accb4c8de7af33083fc2faefb249d87c7de1437c81
SHA256 FW:            9fdfd92f6f1a6e222362b4a9b5110a964df304a66f91e343d25c3be6a88b75c9
Advanced information:
  OEM SRKH:           41a3ab5e956ff6649e843f2686ada51840415d2fa2b6508960098d5bf6f41f27eafeff21a88f3c4b2ccf08895c1440f4b2675fb0bfe5675333b5fcbb3fba9a45
  CSAL state:         EdgeLock secure enclave random context initialization succeed - 0x02
  TRNG state:         TRNG entropy is valid and ready to be read - 0x03
  OEM PQC SRKH:       643dcc626197897115d7cce1ec079c479399af59cd46b9b45b6578fabe86d20e788683151239d8128c4f8ccc871ea86c9d8ee58b6e03e9bf8fdbde6b21b5bd09